ISO7221A-Q1
- 1 and 25Mbps Signaling Rate Options
- Low Channel-to-Channel Output Skew; 1ns Max
- Low Pulse-Width Distortion (PWD); 1ns Max
- Low Jitter Content; 1ns Typ at 25Mbps
- 50kV/µs Typical Transient Immunity
- Operates with 2.8V (C-Grade), 3.3V, or 5V Supplies
- 4kV ESD Protection
- –40°C to +125°C Operating Range
- Typical 28-Year Life at Rated Voltage (see Isolation Lifetime Projection)
- Safety-Related Certifications
- DIN EN IEC 60747-17 (VDE 0884-17)
- UL 1577 component recognition program
- IEC 61010-1, IEC 62368-1 certifications
The ISO7220x-Q1 and ISO7221x-Q1 family devices are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220x-Q1 and in opposite directions in the ISO7221x-Q1. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000VPK per VDE. Used in conjunction with isolated power supplies, these devices block high voltage and isolate grounds, as well as prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to verify that the proper dc level of the output. If this dc-refresh pulse is not received every 4µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from 0Mbps (DC) to 25Mbps (The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps). The A-option, and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS VCC/2 input thresholds and do not have the input noise filter and the additional propagation delay.
The ISO7220x-Q1 and ISO7221x-Q1 family of devices require two supply voltages of 2.8V (C-Grade), 3.3V, 5V, or any combination. All inputs are 5V tolerant when supplied from a 2.8V or 3.3V supply and all outputs are 4mA CMOS.
The ISO7220x-Q1 and ISO7221x-Q1 family of devices are characterized for operation over the ambient temperature range of –40°C to +125°C.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | ISO722x-Q1 Dual-Channel Digital Isolators datasheet (Rev. E) | PDF | HTML | 2024/11/13 |
Certificate | VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. W) | 2024/01/31 | ||
White paper | Improve Your System Performance by Replacing Optocouplers with Digital Isolators (Rev. C) | PDF | HTML | 2023/09/07 | |
Certificate | CSA Certificate for ISO722xD | 2023/03/15 | ||
Certificate | UL Certificate of Compliance File E181974 Vol 4 Sec 1 (Rev. A) | 2022/08/05 | ||
White paper | Why are Digital Isolators Certified to Meet Electrical Equipment Standards? | 2021/11/16 | ||
White paper | Distance Through Insulation: How Digital Isolators Meet Certification Requiremen | PDF | HTML | 2021/06/11 | |
Application brief | How to Replace Optocouplers with Digital Isolators in Standard Interface Circuit (Rev. A) | PDF | HTML | 2021/05/19 | |
EVM User's guide | Universal Digital Isolator Evaluation Module | PDF | HTML | 2021/03/04 | |
Application brief | Considerations for Selecting Digital Isolators | 2018/07/24 |
설계 및 개발
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DIGI-ISO-EVM — 범용 디지털 아이솔레이터 평가 모듈
DIGI-ISO-EVM은 5가지 패키지(8핀 네로우 바디 SOIC(D), 8핀 와이드 바디 SOIC(DWV), 16핀 와이드 바디 SOIC(DW), 16핀 울트라 와이드 바디 SOIC(DWW), 16핀 QSOP(DBQ) 패키지)에서 TI 싱글 채널, 듀얼 채널, 트리플 채널, 쿼드 채널 또는 6채널 디지털 절연기 장치를 평가하는 데 사용되는 평가 모듈(EVM)입니다. EVM에는 최소한의 외부 구성품으로 장치를 평가할 수 있는 충분한 Berg 핀 옵션이 있습니다.
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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