SN54SC4T125-SEP
-
VID V62/23631-01XE
-
Radiation Tolerant
-
Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C
-
Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
-
Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg
-
-
Wide operating range of 1.2 V to 5.5 V
-
Single-supply voltage translator:
-
Up translation:
-
1.2 V to 1.8 V
-
1.5 V to 2.5 V
-
1.8 V to 3.3 V
-
3.3 V to 5.0 V
-
-
Down translation:
- 5.0 V, 3.3 V, 2.5 V to 1.8 V
- 5.0 V, 3.3 V to 2.5 V
- 5.0 V to 3.3 V
-
- 5.5-V tolerant input pins
- Supports standard pinouts
- Up to 150 Mbps with 5-V or 3.3-V V CC
- Latch-up performance exceeds 250 mA per JESD 17
-
Space Enhanced Plastic
-
Controlled baseline
-
Au bondwire and NiPdAu lead finish
-
Meets NASA ASTM E595 outgassing specification
-
One fabrication, assembly, and test site
-
Extended product life cycle
-
Product traceability
-
The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN54SC4T125-SEP Radiation Tolerant, Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet | PDF | HTML | 2023/11/15 |
* | Radiation & reliability report | SN54SC4T125-SEP Single Event Effects Report | PDF | HTML | 2023/12/05 |
* | Radiation & reliability report | SN54SC4T125-SEP Total Ionizing Dose (TID) Report | PDF | HTML | 2023/12/01 |
* | Radiation & reliability report | SN54SC4T125-SEP Production Flow and Reliability Report | PDF | HTML | 2023/11/09 |
Application note | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/07/12 | |
Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/07/03 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
TSSOP (PW) | 14 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치