홈 로직 및 전압 변환 로직 게이트 AND 게이트
홈
로직 및 전압 변환
로직 게이트
AND 게이트

SN74LVC1G08

활성

1채널 2입력 1.65V~5.5V 32mA 드라이브 강도 AND 게이트

지금 주문
데이터 시트

SN74LVC1G08

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
filter 기타 AND 게이트 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품
SN74LVC1G08-Q1 활성 오토모티브, 1채널 2입력 1.65V~5.5V 32mA 드라이브 강도 AND 게이트 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74AUP1G08 활성 1채널, 2입력, 0.8V~3.6V 저전력(< 1uA) AND 게이트 Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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37개 모두 보기
유형 직함 날짜
* Data sheet SN74LVC1G08 Single 2-Input Positive-AND Gate datasheet (Rev. Z) 2019/03/26
Product overview Generate an Enable Signal that can be Toggled PDF | HTML 2023/06/14
Application brief Optimizing Optical Network Terminal Units With Logic PDF | HTML 2023/04/05
Application brief Optimizing Industrial Robot CPU Boards with Logic and Voltage Translation PDF | HTML 2022/12/12
Application brief Optimizing WLAN and WiFi Access Point Systems With Logic and Voltage Translation PDF | HTML 2022/11/03
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Application note Applications of Logic and Translation in IP Cameras (Rev. A) PDF | HTML 2021/03/29
Application note Optimizing HVAC Gateway Designs W/ Common Logic & Translation Voltage Use Cases (Rev. B) PDF | HTML 2021/03/29
Application brief Simplifying Solid-State Relay Designs With Logic PDF | HTML 2021/01/08
Application brief Enable and Disable Digital Signals PDF | HTML 2020/11/04
Application brief Combine Power Good Signals PDF | HTML 2020/10/02
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note Designing and Manufacturing with TI's X2SON Packages 2017/08/23
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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평가 보드

5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈

5~8핀 수의 DCK, DCT, DCU, DRL 또는 DBV 패키지가 있는 모든 디바이스를 지원하도록 설계된 유연한 EVM.
사용 설명서: PDF
TI.com에서 구매 불가
개발 키트

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The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

SN74LVC1G08 Behavioral SPICE Model

SCEM642.ZIP (7 KB) - PSpice Model
다운로드
시뮬레이션 모델

SN74LVC1G08 IBIS Model (Rev. A)

SCEM167A.ZIP (42 KB) - IBIS Model
다운로드

많은 TI 레퍼런스 설계에는 SN74LVC1G08이(가) 포함됩니다.

레퍼런스 디자인 선택 툴을 사용하여 애플리케이션 및 매개 변수에 가장 적합한 설계를 검토하고 식별할 수 있습니다.

레퍼런스 설계 보기
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
DSBGA (YZP) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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