SN74LVC1G38

Name: SN74LVC1G38
Brand: TI
SKU: SN74LVC1G38
Price: 0.056 USD

활성

오픈 드레인 출력을 지원하는 단일 2입력, 1.65V~5.5V NAND 게이트

지금 주문

데이터 시트

document-pdfAcrobat SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output datasheet (Rev. G) (영어) PDF | HTML

SN74LVC1G38

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

8.12 mm² 2.9 x 2.8

4.2 mm² 2 x 2.1

1.45 mm² 1.45 x 1

0.64 mm² 0.8 x 0.8

1 mm² 1 x 1

Latch-up performance exceeds 100 mA Per JESD 78, Class II
ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 200-V Machine model (A115-A)
- 1000-V Charged-device model (C101)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC operation
Inputs accept voltages to 5.5 V
Supports down translation to V_CC
Maximum t_pd of 4.5 ns at 3.3 V
Low power consumption, 10-µA maximum I_CC
±24-mA Output drive at 3.3 V
I_off Supports partial-power-down mode and back-drive protection

Latch-up performance exceeds 100 mA Per JESD 78, Class II
ESD protection exceeds JESD 22
- 2000-V Human-body model (A114-A)
- 200-V Machine model (A115-A)
- 1000-V Charged-device model (C101)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC operation
Inputs accept voltages to 5.5 V
Supports down translation to V_CC
Maximum t_pd of 4.5 ns at 3.3 V
Low power consumption, 10-µA maximum I_CC
±24-mA Output drive at 3.3 V
I_off Supports partial-power-down mode and back-drive protection

The SN74LVC1G38 device is designed for 1.65-V to 5.5-V V_CC operation.

This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC1G38 device is designed for 1.65-V to 5.5-V V_CC operation.

This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

filter

기타 NAND 게이트 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

SN74AUP1G00

활성

단일 1입력, 0.8V~3.6V 저전력 NAND 게이트 Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

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28개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output datasheet (Rev. G)	PDF \| HTML	2018/11/08
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Application note	Designing and Manufacturing with TI's X2SON Packages		2017/08/23
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	User guide	Signal Switch Data Book (Rev. A)		2003/11/14
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		2003/11/06
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		2002/12/18
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002/05/22
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002/03/27
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997/12/01
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997/08/01
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	LVC Characterization Information		1996/12/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits		1996/10/01
	Application note	Live Insertion		1996/10/01
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		1996/09/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01