제품 상세 정보

Function General-purpose timer Iq (typ) (mA) 0.13 Rating Military Operating temperature range (°C) -55 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
Function General-purpose timer Iq (typ) (mA) 0.13 Rating Military Operating temperature range (°C) -55 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Very Low Power Consumption...2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally interchangeable With the NE556; Has Same Pinout

LinCMOS is a trademark of Texas Instruments Incorporated.

  • Very Low Power Consumption...2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally interchangeable With the NE556; Has Same Pinout

LinCMOS is a trademark of Texas Instruments Incorporated.

The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and

a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from -40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of -55°C to 125°C

The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and

a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from -40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of -55°C to 125°C

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기술 자료

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2개 모두 보기
유형 직함 날짜
* Data sheet Dual LinCMOS Timers datasheet (Rev. B) 1997/09/25
* SMD TLC556M SMD 5962-89503 2016/06/21

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

TLC555x and TLC556x PSpice Model (Rev. E)

SLFJ002E.ZIP (25 KB) - PSpice Model
시뮬레이션 모델

TLC556 TINA-TI Astable Reference Design

SLFM008.TSC (100 KB) - TINA-TI Reference Design
시뮬레이션 모델

TLC556 TINA-TI Mono Reference Design

SLFM006.TSC (102 KB) - TINA-TI Reference Design
시뮬레이션 모델

TLC556 TINA-TI Spice Model (Rev. A)

SLFM001A.ZIP (9 KB) - TINA-TI Spice Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

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