TXV0108-Q1
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Configurable design allows each port to operate with a power supply range from 1.14V to 3.6V
- Supports up to 500Mbps for 1.65V to 3.6V
- AEC-Q100 qualified for automotive applications
- Meets RGMII 2.0 timing specifications:
- < 750ps rise and fall time
- < ± 5 % duty cycle distortion
- < ± 400ps channel to channel skew
- Up to 250Mbps/channel
- Integrated 10Ω damping output resistor to minimize signal reflections
- High drive strength (up to 12mA at 3.6V)
- Fully configurable symmetric dual-rail design
- Optimal signal integrity performance with 390ps peak-to-peak jitter for 1.8V to 3.3V
- Features VCC isolation and VCC disconnect
- Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD protection exceeds JESD 22:
- 2000-V Human-Body Model
- 1000-V Charged-Device Model
- Low power consumption:
- 10µA maximum (25°C)
- 20µA maximum (–40°C to 125°C)
- Operating temperature from –40°C to +125°C
- Pin compatible with SN74AVC8T245 (VQFN)
- Available in wettable flank VQFN (RGY) package
The TXV0108-Q1 is an 8-bit, dual-supply direction controlled low-skew, low-jitter voltage translation device. This device can be used for redriving, voltage translation, and power isolation when implementing skew sensitive interface, such as RGMII between Ethernet MAC and PHY devices. The Ax I/O pins and control pins (DIR, OE) are referenced to VCCA logic levels, and Bx I/O pins are referenced to VCCB logic levels. This device has improved channel-to-channel skew, duty cycle distortion and symmetric rise and fall time for applications requiring strict timing conditions.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature is designed so that if either VCC supply is at or near 0V both ports will switch to a high-impedance state. This feature enables power isolation for communications across multiple MACs and PHYs, and is beneficial in situations where MACs and PHYs are powered up asynchronously preventing current backflow between devices.
A High on DIR allows data transmission from A to B while a Low on DIR allows data transmission from B to A when OE is set to Low. When OE is set to High, both Ax and Bx pins will be forced into a high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.
관심 가지실만한 유사 제품
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈
14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.
TXV0108-EVM — TXV0108 평가 모듈
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
VQFN (RGY) | 24 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치