LM2502

ACTIVE

Mobile pixel link (MPL) display interface serializer and deserializer

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -30 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -30 to 85
WQFN (RSB) 40 25 mm² 5 x 5
  • >300 Mbps Dual Link Raw Throughput
  • MPL Physical Layer (MPL-0)
  • Pin Selectable Master / Slave Mode
  • Frequency Reference Transport
  • Complete LVCMOS / MPL Translation
  • Interface Modes:
    • 16-bit CPU, i80 or m68 Style
    • RGB565 with Glue Logic
  • −30°C to 85°C Operating Range
  • Link Power Down Mode Reduces IDDZ < 10 µA
  • Dual Display Support (CS1* & CS2*)
  • Via-less MPL Interconnect Feature
  • 3.0V Supply Voltage (VDD and VDDA)
  • Interfaces to 1.7V to 3.3V Logic (VDDIO)

All trademarks are the property of their respective owners.

  • >300 Mbps Dual Link Raw Throughput
  • MPL Physical Layer (MPL-0)
  • Pin Selectable Master / Slave Mode
  • Frequency Reference Transport
  • Complete LVCMOS / MPL Translation
  • Interface Modes:
    • 16-bit CPU, i80 or m68 Style
    • RGB565 with Glue Logic
  • −30°C to 85°C Operating Range
  • Link Power Down Mode Reduces IDDZ < 10 µA
  • Dual Display Support (CS1* & CS2*)
  • Via-less MPL Interconnect Feature
  • 3.0V Supply Voltage (VDD and VDDA)
  • Interfaces to 1.7V to 3.3V Logic (VDDIO)

All trademarks are the property of their respective owners.

The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.

The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module.

Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface.

The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current.

The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) NFBGA and WQFN packages.

The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.

The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module.

Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface.

The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current.

The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) NFBGA and WQFN packages.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer datasheet (Rev. L) 02 May 2013
Application note Mobile Pixel Link Level-0 20 Mar 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins CAD symbols, footprints & 3D models
WQFN (RSB) 40 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos