CD4011UB-MIL
- Propagation delay time = 30 ns (typ). at CL = 50 pF, VDD = 10 V
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of 1 µA at 18 V over full package temperature range; 100nA at 18 V and 25°C
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B "Standard Specifications for Description of ’B’ Series CMOS Devices"
Data sheet acquired from Harris Semiconductor
CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates.
The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
技術文件
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檢視所有 1 類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CD4011UB TYPES datasheet (Rev. D) | 2003年 8月 21日 |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點