程式碼範例或展示
CDCM6208
- Superior Performance With Low Power:
- Low Noise Synthesizer (265 fs-rms Typical Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms Typical Jitter)
- 0.5-W Typical Power Consumption
- High Channel-to-Channel Isolation and Excellent PSRR
- Device Performance Customizable Through Flexible 1.8-V, 2.5-V and 3.3-V Power Supplies, Allowing Mixed Output Voltages
- Flexible Frequency Planning:
- 4x Integer Down-Divided Differential Clock Outputs Supporting LVPECL-Like, CML, or LVDS-Like Signaling
- 4x Fractional or Integer Divided Differential Clock Outputs Supporting HCSL, LVDS-Like Signaling, or Eight CMOS Outputs
- Fractional Output Divider Achieve 0 ppm to < 1 ppm Frequency Error and Eliminates Need for Crystal Oscillators and Other Clock Generators
- Output Frequencies up to 800 MHz
- Two Differential Inputs, XTAL Support, Ability for Smart Switching
- SPI, I2C, and Pin Programmable
- Professional User GUI for Quick Design Turnaround
- 7 × 7 mm 48-VQFN package (RGZ)
- –40°C to 85°C Temperature Range
The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, Small Cells, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208 also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208 can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.
技術文件
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檢視所有 7 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCM6208 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers datasheet (Rev. G) | PDF | HTML | 2018年 1月 9日 |
| Application note | How to measure Total Jitter (TJ) (Rev. B) | 2017年 8月 8日 | ||
| Technical article | The five benefits of multifaceted clocking devices | PDF | HTML | 2016年 5月 17日 | |
| Application note | Crystal or Crystal Oscillator Replacement with Silicon Devices | 2014年 6月 18日 | ||
| EVM User's guide | CDCM6208 EVM User's Guide (Rev. A) | 2012年 12月 19日 | ||
| Application note | Driving the TLK10002 10Gpbs SERDES with the CDCM6208 Clock Generator | 2012年 12月 14日 | ||
| Application note | A Step by Step Guide on Using the MSP430 as a Bootloader for the CDCM6208VxEVM (Rev. A) | 2012年 12月 4日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
CDCM6208V1EVM — CDCM6208V1 評估模組
The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, (...)
使用指南: PDF
開發板
CDCM6208V2EVM — CDCM6208V2 評估模組
The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, (...)
使用指南: PDF
開發套件
EVMK2GX — 66AK2Gx 1GHz 評估模組
The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)
使用指南: PDF
開發套件
EVMK2GXS — 66AK2Gx (K2G) 1 GHz 高安全性評估模組
The K2G 1GHz High Secure Evaluation Module (EVM) enables developers to start evaluating and testing the programming of the high secure developmental version of the 66AK2Gx processor, and to accelerate the next stage of secure boot product development of audio and industrial real (...)
使用指南: PDF
韌體
SLAC550 — CDCM6208EVM - I2C Firmware Update Files
支援產品和硬體
產品
時鐘產生器
硬體開發
開發板
開發模組 (EVM) 的 GUI
SCAC134 — CDCM6208 EVM Control GUI
支援產品和硬體
產品
時鐘產生器
硬體開發
開發板
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDEP0069 — 66AK2Gx DSP + ARM 處理器音訊處理參考設計
This reference design is a reference platform based on the 66AK2Gx DSP + ARM processor System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software (...)
參考設計
TIDEP0067 — 66AK2Gx DSP + ARM 處理器電源解決方案參考設計
This reference design is based on the 66AK2Gx multicore System-on-Chip (SoC) processor and companion TPS65911 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2Gx processor in a single device. This power solution design also includes (...)
參考設計
TIDEP0068 — 適用於 K2G 通用 EVM (GP EVM) 的 PCI-Express PCB 設計注意事項參考設計
PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2Gx DSP + ARM Processor system on chip (SoC). This PCIe PCB design considerations reference design (...)
參考設計
TIDEP0070 — 用於在 66AK2Gx 系統中提高記憶體可靠性的 DDR ECC 參考設計
This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high (...)
參考設計
TIDA-00352 — SDI 視訊聚合參考設計
This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
參考設計
TIDA-00309 — DisplayPort 視訊 4:1 聚合參考設計
This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
參考設計
TIDA-00269 — Gigabit 乙太網路鏈路聚合器參考設計
The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
參考設計
TIDA-00234 — 適用於具有兩個或多個 SFP+ 光學連接埠之系統的雙通道 XAUI 到 SFI 參考設計
The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。