LMK61E2-100M
- Ultra-low Noise, High Performance
- Jitter: 90 fs RMS Typical Fout > 100 MHz
- PSRR: –70 dBc, Robust Supply Noise Immunity
- Supported Output Format
- LVPECL up to 1 GHz
- LVDS up to 900 MHz
- HCSL up to 400 MHz
- Total Frequency Tolerance of ± 50 ppm (LMK61X2) and ± 25 ppm (LMK61X0)
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7 mm × 5 mm 6-Pin Package, Pin-Compatible With Industry Standard 7050 XO Package
The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMK61XX High-Performance Ultra-Low Jitter Oscillator datasheet (Rev. D) | PDF | HTML | 2017年 10月 19日 |
| EVM User's guide | LMK61FFEVM User's Guide (Rev. A) | 2015年 11月 20日 |
設計與開發
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LMK61E2-100M00EVM — LMK61E2-100M00EVM 超低抖動固定頻率振盪器 EVM
The LMK61E2-100M00EVM evaluation module provides a complete platform to evaluate the 90-fs RMS jitter performance of Texas Instruments LMK61E2-100M00 Ultra-Low Jitter Fixed Frequency Oscillator.
The onboard power supply options allow for ease of use as well as configuration flexibility required in (...)
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFM (SIA) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
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