LMK04808
- Ultra-Low RMS Jitter Performance
- 111 fs RMS Jitter (12 kHz to 20 MHz)
- 123 fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator
Circuit - Holdover Mode when Input Clocks are Lost
- Automatic or Manual Triggering/Recovery
- Integrated Low-Noise Crystal Oscillator
- PLL2
- Normalized PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Integrated Low-Noise VCO
- 2 Redundant Input Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd) - 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs - Digital Delay: Fixed or Dynamically Adjustable
- 25 ps Step Analog Delay Control.
- 14 Differential Outputs. Up to 26 Single Ended.
- Up to 6 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 1536 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution - Industrial Temperature Range: –40 to 85°C
- 3.15-V to 3.45-V Operation
- 2 Dedicated Buffered/Divided OSCin Clocks
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK0480x family is the industrys highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 2014年 12月 24日 |
User guide | TSW308x Evaluation Module (Rev. B) | 2016年 5月 18日 | ||
EVM User's guide | TSW4806EVM User's Guide (Rev. A) | 2016年 4月 26日 | ||
EVM User's guide | LMK0480x Evaluation Board Instructions (Rev. B) | 2014年 8月 4日 | ||
Design guide | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 2013年 9月 3日 | ||
Application note | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 2013年 7月 12日 | ||
Application note | Effects of Clock Noise on High Speed DAC Performance | 2012年 11月 8日 | ||
User guide | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 2011年 12月 29日 | ||
Design guide | Clock Conditioner Owner's Manual | 2006年 11月 10日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
TSW1265EVM — 寬頻雙路接收器參考設計和評估平台
The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)
TSW3084EVM — 寬頻發射訊號鏈評估板和參考設計
The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)
TSW30H84EVM — 寬頻發射訊號鏈評估板和參考設計
The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution (...)
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
支援產品和硬體
產品
時鐘產生器
時鐘緩衝器
時鐘抖動清除器
RF PLL 與合成器
硬體開發
開發板
CLOCKDESIGNTOOL — Clock Design Tool Software
The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
支援產品和硬體
產品
時鐘產生器
時鐘緩衝器
時鐘抖動清除器
RF PLL 與合成器
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
支援產品和硬體
產品
時鐘緩衝器
時鐘產生器
時鐘抖動清除器
時脈網路同步器
RF PLL 與合成器
IQ 解調器
硬體開發
開發板
軟體
應用軟體及架構
IDE、配置、編譯器或偵錯程式
支援軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
WQFN (NKD) | 64 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。