LMK61PD0A2
- Ultra-low Noise, High Performance
- Jitter: 90 fs RMS typical fOUT > 100 MHz
- PSRR: –70 dBc, robust supply noise immunity
- Flexible Output Frequency and Format; User
Selectable- Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz,
125 MHz, 156.25 MHz, 212.5 MHz,
312.5 MHz - Formats: LVPECL, LVDS or HCSL
- Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz,
- Total frequency tolerance of ± 50 ppm
- Internal memory stores multiple start-up
configurations, selectable through pin control - 3.3V operating voltage
- Industrial temperature range (–40ºC to +85ºC)
- 7 mm × 5 mm 8-pin package
The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator datasheet (Rev. A) | PDF | HTML | 2015年 11月 3日 |
| EVM User's guide | LMK61PDEVM User's Guide (Rev. A) | 2015年 11月 20日 |
設計與開發
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LMK61PDEVM — LMK61PDEVM 超低抖動針腳可選擇振盪器 EVM
The LMK61PDEVM evaluation modules provides a complete platform to evaluate the 100-fs RMS jitter performance and configurability of the Texas Instruments LMK61PD Ultra-Low Jitter Pin Selectable Differential Oscillator with 7 unique reference clock frequencies and configurable output format.
The (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFM (SIA) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。