LMK60E0-156M
- Low Noise, High Performance
- Jitter: 150 fs RMS Typical Fout > 100 MHz
- PSRR: –60 dBc, Robust Supply Noise Immunity
- Supported Output Format
- LVPECL, LVDS and HCSL up to 400 MHz
- Total Frequency Tolerance of ±50 ppm (LMK60X2) and ±25 ppm (LMK60X0)
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 6-pin Package That is Pin-Compatible With Industry Standard 7050 XO Package
The LMK60EX is a family of low jitter oscillators that generate a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL, LVDS, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ±5% supply.
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMK60XX High Performance Low Jitter Oscillator datasheet (Rev. C) | PDF | HTML | 2017年 11月 30日 |
| EVM User's guide | LMK60XXEVM, LMK62XXEVM User's Guide (Rev. A) | 2017年 2月 9日 |
設計與開發
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設計工具
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFM (SIA) | 6 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點