LMK03328
- Ultra Low Noise, High Performance
- Jitter: 100-fs RMS Typical, FOUT > 100 MHz
- PSNR: –80 dBc, Robust Supply Noise Immunity
- Flexible Device Options
- Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
- Pin Mode, I2C Mode, and EEPROM Mode
- 71-Pin Selectable Pre-Programmed Default Start-Up Options
- Dual Inputs With Automatic or Manual Selection
- Crystal Input: 10 to 52 MHz
- External Input: 1 to 300 MHz
- Frequency Margining Options
- Fine Frequency Margining (±50 ppm Typical) Using Low-Cost Pullable Crystal Reference
- Glitchless Coarse Frequency Margining (%) Using Output Dividers
- Other Features
- Supply: 3.3-V Core, 1.8-V, 2.5-V, 3.3-V Output Supply
- Industrial Temperature Range (–40ºC to +85ºC)
- Package: 7-mm × 7-mm 48-WQFN
The LMK03328 device is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.
For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.
All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.
All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.
The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable through pin control and can eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs are settable with a 3-state pin.
The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.
Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5% supply.
您可能會感興趣的類似產品
功能相同,但引腳輸出與所比較的裝置不同
技術文件
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK03328EVM — 具有 2 個 PLL、8 個差動輸出和 2 個輸入的 LMK03328EVM 超低抖動時鐘產生器 EVM
The LMK03328EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03328 Ultra-Low-Jitter Clock Generator with Dual PLLs, 8 outputs, 2 inputs, and integrated EEPROM.
The (...)
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
支援產品和硬體
產品
時鐘產生器
RF PLL 與合成器
時鐘緩衝器
振盪器
時鐘抖動清除器
時脈網路同步器
硬體開發
開發板
軟體
IDE、配置、編譯器或偵錯程式
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
支援產品和硬體
產品
RF PLL 與合成器
時鐘緩衝器
時鐘產生器
IQ 解調器
時鐘抖動清除器
時脈網路同步器
硬體開發
開發板
軟體
應用軟體及架構
IDE、配置、編譯器或偵錯程式
支援軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
WQFN (RHS) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。