產品詳細資料

Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 25 Supply voltage (V) 3.3 Jitter (ps) 0.09 Operating temperature range (°C) -40 to 85
Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 25 Supply voltage (V) 3.3 Jitter (ps) 0.09 Operating temperature range (°C) -40 to 85
QFM (SIA) 6 35 mm² 7 x 5
  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E08
    • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
  • Flexible Output Format on LMK61E08
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 6-Pin Package
  • Default Frequency:
    • 70.656 MHz
  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E08
    • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
  • Flexible Output Format on LMK61E08
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 6-Pin Package
  • Default Frequency:
    • 70.656 MHz

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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* Data sheet LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet PDF | HTML 2020年 6月 24日

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LMK61E2EVM — LMK61E2EVM 超低抖動且可程式編輯之振盪器的評估模組

The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.

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