SN54SC4T32-SEP

現行

具有整合式位準移位器的耐輻射、四通道、二輸入 1.2-V 至 5.5-V OR 閘

產品詳細資料

Technology family SCxT Number of channels 4 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
Technology family SCxT Number of channels 4 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/23629-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:
        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/23629-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:
        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC4T32-SEP contains four independent 2-input OR Gates with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

The SN54SC4T32-SEP contains four independent 2-input OR Gates with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 5
類型 標題 日期
* Data sheet SN54SC4T32-SEPRadiation Tolerant, Quadruple 2-Input Positive-OR Gates With Integrated Translation datasheet PDF | HTML 2023年 11月 15日
* Radiation & reliability report SN54SC4T32-SEP Total Ionizing Dose (TID) Report PDF | HTML 2023年 12月 13日
* Radiation & reliability report SN54SC4T125-SEP Single Event Effects Report PDF | HTML 2023年 12月 5日
* Radiation & reliability report SN54SC4T32-SEP Production Flow and Reliability Report PDF | HTML 2023年 11月 14日
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024年 9月 10日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
TI.com 無法提供
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 14 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片