SN74AUC02

Name: SN74AUC02
Brand: TI
SKU: SN74AUC02
Price: 0.139 USD

現行

4 通道、2 輸入、0.8-V 至 2.7-V 高速 NOR 閘

立即訂購

產品規格表

document-pdfAcrobat SN74AUC02 datasheet (Rev. A) (英文)

SN74AUC02

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUC

Number of channels

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-9

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

250

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Number of channels

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-9

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

250

Rating

Catalog

Operating temperature range (°C)

-40 to 85

VQFN (RGY)

12.25 mm² 3.5 x 3.5

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 2.2 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 2.2 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

This quadruple 2-input positive-NOR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC02 device performs the Boolean function Y = (A + B)\ or Y = A\ × B\ in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This quadruple 2-input positive-NOR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC02 device performs the Boolean function Y = (A + B)\ or Y = A\ × B\ in positive logic.

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現行

4 通道、2 輸入、1.5-V 至 3.6-V NOR 閘 Higher average drive strength (24mA), longer average propagation delay (5.5ns)

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	類型	標題	日期
*	Data sheet	SN74AUC02 datasheet (Rev. A)	2005年 3月 29日
	Selection guide	Little Logic Guide 2018 (Rev. G)	2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)	2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)	2003年 11月 14日
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices	2003年 3月 21日
	User guide	AUC Data Book, January 2003 (Rev. A)	2003年 1月 1日
	Application note	Texas Instruments Little Logic Application Report	2002年 11月 1日
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