SN74AUP2G08

Name: SN74AUP2G08
Brand: TI
SKU: SN74AUP2G08
Price: 0.123 USD

現行

2 通道、2 輸入、0.8V 至 3.6V 低功耗 (< 1uA) AND 閘

立即訂購

產品規格表

document-pdfAcrobat SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. E) (英文) PDF | HTML

SN74AUP2G08

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YFP)

1.8 mm² 1 x 1.8

DSBGA (YZP)

2.8125 mm² 2.25 x 1.25

UQFN (RSE)

2.25 mm² 1.5 x 1.5

VSSOP (DCU)

6.2 mm² 2 x 3.1

X2SON (DQE)

1.4 mm² 1.4 x 1

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

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SN74LVC2G08

現行

2 通道、2 輸入、1.65V 至 5.5V 32mA 驅動強度 AND 閘 Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)

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	類型	標題		日期
*	Data sheet	SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. E)	PDF \| HTML	2024年 4月 29日
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	2019年 5月 22日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日