產品詳細資料

Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 1000 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 1000 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C

    • Device HBM ESD classification level 2

    • Device CDM ESD classification level C4B

  • Wide operating range of 1.8V to 5.5V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:

      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C

    • Device HBM ESD classification level 2

    • Device CDM ESD classification level C4B

  • Wide operating range of 1.8V to 5.5V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:

      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV1T00-Q1 is a 2-input NAND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV1T00-Q1 is a 2-input NAND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

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* Data sheet SN74LV1T00-Q1 Automotive 2-Input Positive-NAND Gates With Integrated Translation datasheet (Rev. A) PDF | HTML 2024年 1月 19日

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