SN74LV1T08-Q1
-
AEC-Q100 qualified for automotive applications:
-
Device temperature grade 1: -40°C to +125°C
-
Device HBM ESD classification level 2
-
Device CDM ESD classification level C4B
-
- Wide operating range of 1.8 V to 5.5 V
-
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
-
Up translation:
-
1.2-V to 1.8-V
-
1.5-V to 2.5-V
-
1.8-V to 3.3-V
-
3.3-V to 5.0-V
-
-
Down translation:
- 5.0-V, 3.3-V, 2.5-V to 1.8-V
- 5.0-V, 3.3-V to 2.5-V
- 5.0-V to 3.3-V
-
- 5.5-V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5-V or 3.3-V VCC
- Latch-up performance exceeds 250 mAper JESD 17
The SN74LV1T08-Q1 is a 2-input AND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3-V to 2.5-V output).
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | SN74LV1T08-Q1 Automotive 2-Input Positive-AND Gates With Integrated Translation datasheet (Rev. A) | PDF | HTML | 2024年 1月 19日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOT-23 (DBV) | 5 | Ultra Librarian |
SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點