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SN74LV27A

現行

3 通道、3 輸入、2-V 至 5.5-V NOR 閘

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產品規格表

SN74LV27A

現行
產品規格表 立即訂購

產品詳細資料

Technology family LV-A Number of channels 3 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Inputs per channel 3 IOL (max) (mA) 12 IOH (max) (mA) -12 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LV-A Number of channels 3 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Inputs per channel 3 IOL (max) (mA) 12 IOH (max) (mA) -12 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • Operation of 2-V to 5.5-V V CC
  • Max t pd of 7 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Operation of 2-V to 5.5-V V CC
  • Max t pd of 7 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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* Data sheet SN74LV27A Triple 3-Input Positive-NOR Gate datasheet (Rev. F) PDF | HTML 2023年 7月 14日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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模擬型號

SN74LV27A Behavioral SPICE Model

SCEM651.ZIP (8 KB) - PSpice Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

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