SN74LVC1G86-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to VCC
- Low Power Consumption, 15-µA Maximum ICC
- Maximum tpd of 6 ns at 3.3 V and 50-pF load
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode, and Back-Drive Protection
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 6 ns at 3.3 V and 50-pF capacitive load. The max output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.
技術文件
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點