SBAA565 November   2022 ADC081C021 , ADC081C027 , ADC101C021 , ADC101C027 , ADC121C021 , ADC121C021-Q1 , ADC121C027 , ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1014 , ADS1015 , ADS1015-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1114 , ADS1115 , ADS1115-Q1 , ADS7823 , ADS7827 , ADS7828 , ADS7828-Q1 , ADS7830 , ADS7924 , AFE539A4 , DAC081C081 , DAC081C085 , DAC101C081 , DAC101C081Q , DAC101C085 , DAC121C081 , DAC121C085 , DAC43204 , DAC43401 , DAC43401-Q1 , DAC43608 , DAC43701 , DAC43701-Q1 , DAC53002 , DAC53004 , DAC53202 , DAC53204 , DAC53204W , DAC53401 , DAC53401-Q1 , DAC53608 , DAC53701 , DAC53701-Q1 , DAC5571 , DAC5573 , DAC5574 , DAC5578 , DAC60501 , DAC60502 , DAC63002 , DAC63004 , DAC63202 , DAC63204 , DAC6571 , DAC6573 , DAC6574 , DAC6578 , DAC70501 , DAC70502 , DAC7571 , DAC7573 , DAC7574 , DAC7578 , DAC7678 , DAC80501 , DAC80502 , DAC8571 , DAC8574

 

  1.   Abstract
  2.   Trademarks
  3. 1I2C Overview
    1. 1.1 History
    2. 1.2 I2C Speed Modes
  4. 2I2C Physical Layer
    1. 2.1 Two-Wire Communication
    2. 2.2 Open-Drain Connection
    3. 2.3 Non-Destructive Bus Contention
  5. 3I2C Protocol
    1. 3.1 I2C START and STOP
    2. 3.2 Logical Ones and Zeros
    3. 3.3 I2C Communication Frames
  6. 4I2C Examples
    1. 4.1 DAC80501 Example
      1. 4.1.1 DAC80501 DAC Data Register
      2. 4.1.2 DAC80501 I2C Example Write
    2. 4.2 ADS1115 Example
      1. 4.2.1 ADS1115 Configuration Register
      2. 4.2.2 ADS1115 I2C Example Read
      3. 4.2.3 ADS1115 Conversion Result
  7. 5Reserved Addresses
    1. 5.1 General Call
    2. 5.2 START Byte
    3. 5.3 C-Bus Address, Different Bus Format, Future Purposes
    4. 5.4 HS-Mode Controller Code
    5. 5.5 Device ID
    6. 5.6 10-Bit Target Addressing
      1. 5.6.1 10-Bit Target Addressing Write
      2. 5.6.2 10-Bit Target Addressing Read
  8. 6Advanced Topics
    1. 6.1 Clock Synchronization and Arbitration
    2. 6.2 Clock Stretching
    3. 6.3 Electrical Specifications
    4. 6.4 Voltage Level Translation
      1. 6.4.1 Example 1
      2. 6.4.2 Example 2
      3. 6.4.3 Example 3
      4. 6.4.4 Example 4
    5. 6.5 Pullup Resistor Sizing
      1. 6.5.1 Minimum Pullup Resistance Sizing
      2. 6.5.2 Maximum Pullup Resistance Sizing
  9. 7Protocols Similar to I2C
  10. 8Summary

5.4 HS-Mode Controller Code

The next reserved addresses are for the high-speed controller code. These codes are from 04 to 07. The eighth bit normally used for read or write indication is used as part of the high-speed controller code. These high-speed controller codes are reserved 8-bit codes which are not used for target addressing or other purposes. Each high-speed controller has a unique controller code and this allows for up to eight high-speed controllers on the I2C bus. The controller code for a high-speed mode controller device is software programmable and is chosen by the system designer.

Devices that support high-speed mode begin operation in standard or fast mode. The controller code enables high-speed mode. The high-speed controller code allows for arbitration between the high-speed controllers and indicates the start of a high-speed mode transfer. The code enables internal current sources allowing the I2C communication bus to be faster than with just pullup resistors.

When enabled, high-speed data transfer continues through the data transmission. A repeated START continues high-speed mode data transmission, while a STOP condition returns the I2C bus to fast or standard mode. Figure 5-2 shows the start transmission to the high-speed controller code. This diagram shows the beginning of a high-speed mode transmission.

Figure 5-2 I2C High-Speed Controller Code

For this and subsequent byte and bit frame diagrams, the shaded codes are set by the controller device, while the non-shaded codes are set by the target device.

At the start of communication, the device starts in standard or fast mode. The controller sends a START condition by pulling SDA low followed by pulling SCL low. Then, the first byte is sent with the reserved address used for the high-speed controller code. The controller code enables high-speed mode for all devices that are capable of high-speed mode, and the internal circuits of the controller for high-speed mode are enabled. Figure 5-3 shows a detailed figure on how the I2C high-speed mode is enabled followed by communication with data.

Figure 5-3 Enabling I2C High-Speed Mode

The controller then sends the target address of the high-speed mode device and follows with a read or write bit for communication. Data is transmitted by the controller or target, with ACK for each data byte similar to the standard I2C communication. The target device continues communication until receiving a STOP condition or receiving a repeated START for a new target address.