CY74FCT823T

Name: CY74FCT823T
Brand: TI
SKU: CY74FCT823T
Price: 0.432 USD

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Flipflops, Bus-Schnittstelle mit 9 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 9-Bit Bus-Interface Register With 3-State Outputs datasheet (Rev. A) (Englisch)

CY74FCT823T

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Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

9

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

200

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

9

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

200

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

SSOP (DBQ)

24

51.9 mm² 8.65 x 6

Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823
Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
64-mA Output Sink Current
32-mA Output Source Current
High-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops
Buffered Common Clock-Enable (EN\) and Asynchronous-Clear (CLR\) Inputs
3-State Outputs

Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823
Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
64-mA Output Sink Current
32-mA Output Source Current
High-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops
Buffered Common Clock-Enable (EN\) and Asynchronous-Clear (CLR\) Inputs
3-State Outputs

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high I_OL/I_OH.

This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high I_OL/I_OH.

This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 8

	Typ	Titel	Datum
*	Data sheet	9-Bit Bus-Interface Register With 3-State Outputs datasheet (Rev. A)	02 Nov 2001
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	CYFCT Parameter Measurement Information	02 Apr 2001
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 Jan 2001

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
SOIC (DW)	24	Ultra Librarian
SSOP (DBQ)	24	Ultra Librarian

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CY74FCT823T

Flipflops, Bus-Schnittstelle mit 9 Bit, mit Tri-State-Ausgängen

CY74FCT823T

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