SN74LVC1G0832

Name: SN74LVC1G0832
Brand: TI
SKU: SN74LVC1G0832
Price: 0.075 USD

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Einfaches Positiv UND-ODER-Gatter mit 3 Eingängen

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Datenblatt

document-pdfAcrobat SN74LVC1G0832 datasheet (Rev. D) (Englisch)

SN74LVC1G0832

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Datenblatt

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Produktdetails

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

1

Inputs per channel

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

1

Inputs per channel

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

6

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

6

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

6

4.2 mm² 2 x 2.1

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ @ 3.3 V)
Can Be Used in Three Combinations:
- AND-OR Gate
- AND Gate
- OR Gate
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ @ 3.3 V)
Can Be Used in Three Combinations:
- AND-OR Gate
- AND Gate
- OR Gate
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This device is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.

By tying one input to GND or V_CC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V_CC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to V_CC (Y = A + C).

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This device is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.

By tying one input to GND or V_CC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V_CC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to V_CC (Y = A + C).

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 27

	Typ	Titel	Datum
*	Data sheet	SN74LVC1G0832 datasheet (Rev. D)	24 Nov 2013
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	06 Nov 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	18 Dez 2002
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 Mai 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 Mai 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 Mär 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	LVC Characterization Information	01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 Mai 1996

Design und Entwicklung

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Benutzerhandbuch: PDF

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Simulationsmodell

SN74LVC1G0832 IBIS Model (Rev. A)

SCEM473A.ZIP (44 KB) - IBIS Model

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
DSBGA (YZP)	6	Ultra Librarian
SOT-23 (DBV)	6	Ultra Librarian
SOT-SC70 (DCK)	6	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

SN74LVC1G0832

Einfaches Positiv UND-ODER-Gatter mit 3 Eingängen

SN74LVC1G0832

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5-8-LOGIC-EVM — Generisches Logik-Evaluierungsmodul für 5- bis 8-polige DCK-, DCT-, DCU-, DRL- und DBV-Gehäuse

SN74LVC1G0832 IBIS Model (Rev. A)

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