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Digitale Signalprozessoren (DSPs)

TMS320C5504

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C55x Festkomma-DSP mit geringem Stromverbrauch – bis zu 150 MHz, USB

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TMS320C5504

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Produktdetails

DSP type 1 C55x DSP (max) (MHz) 100, 120, 150 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 1 C55x DSP (max) (MHz) 100, 120, 150 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-, 150-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 256K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 192K Bytes of Single-Access RAM (SARAM), 24 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL)
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-, 150-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 256K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 192K Bytes of Single-Access RAM (SARAM), 24 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL)
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet TMS320C5504 Fixed-Point Digital Signal Processor datasheet (Rev. G) 13 Aug 2013
* Errata TMS320C5505/C5504 Fixed-Point DSP Silicon Errata (Silicon Revision 2.0) (Rev. D) 15 Jul 2015
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 Mai 2021
Application note Using the TMS320C5515/14/05/04 Bootloader (Rev. D) 25 Nov 2019
Application note Power Estimation and Pwr Consumption Sum for TMS320C5504/05/14/15/32/33/34/35/45 (Rev. A) 04 Apr 2016
Application note C5000 DSP-Based Low-Power System Design 30 Nov 2015
User guide TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 30 Sep 2015
User guide TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (Rev. A) 03 Okt 2013
User guide TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 18 Nov 2012
User guide TMS320C5515/14/05/04 DSP Real-Time Clock (RTC) User's Guide (Rev. A) 15 Nov 2012
User guide TMS320C5504 DSP System User's Guide (Rev. C) 14 Sep 2012
User guide TMS320C5515/14/05/04 DSP Inter-IC Sound (I2S) Bus User's Guide (Rev. B) 09 Aug 2012
User guide TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (Rev. A) 07 Mär 2012
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. I) 09 Nov 2011
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 09 Nov 2011
Product overview C5515 eZdsp (Rev. A) 08 Nov 2010
Product overview TMS320C5504, TMS320C5505, TMS320C5515 and TMS320C5514 Product Bulletin 12 Jan 2010
User guide TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output User's Guide 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Inter-Integrated Circuit (I2C) Peripheral UG (Rev. A) 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Serial Peripheral Interface (SPI) UG 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP UART User's Guide 21 Sep 2009
User guide TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 24 Jun 2009
User guide TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 24 Jun 2009
User guide TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 17 Jun 2009
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. H) 31 Jul 2004
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. F) 31 Dez 2003

Design und Entwicklung

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Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Die XDS200 ist eine Debug-Sonde (Emulator) zum Debuggen von Embedded-Bausteinen von TI. Die XDS200 bietet ein ausgewogenes Preis-Leistungsverhältnis im Vergleich zum preiswerten XDS110 und dem leistungsstarken XDS560v2 und unterstützt zahlreiche Standards (IEEE1149,1, IEEE1149,7, SWD) in einem (...)

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Anwendungssoftware und Frameworks

C55X-USBAUDIO — C55x USB Audio Class Framework

The TMS320C55x™ Connected Audio Framework provides a software framework which allows the C55x devices to operate as a USB Audio peripheral. In addition to providing this capability, the framework can be extended by users by the incorporation of audio processing algorithms in the record and (...)
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TMS320C5504 — C55x Festkomma-DSP mit geringem Stromverbrauch – bis zu 150 MHz, USB TMS320C5505 — Energieeffizienter C55x Festkomma-DSP – bis zu 150MHz, USB, LCD-Schnittstelle, FFT HWA, SAR ADC TMS320C5514 — C55x Festkomma-DSP mit geringem Stromverbrauch – bis zu 120 MHz, USB TMS320C5515 — C55x Festkomma-DSP – bis zu 120 MHz, USB, LDC-Schnittstelle, FFT HWA, SAR ADC mit geringem Stromverb
Download-Optionen
Treiber oder Bibliothek

C55XCSL-LOWPOWER — TMS320C55x Chip Support Library for C5504/05, C5514/15/17 and C5535/45 devices

The C55x Chip Support Libraries (CSL) provide an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C55x devices and hardware abstraction. CSLs will shorten development time by providing (...)

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Digitale Signalprozessoren (DSPs)
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Download-Optionen
Treiber oder Bibliothek

SPRC100 — TMS320C55x DSP-Bibliothek (DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
Benutzerhandbuch: PDF
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Treiber oder Bibliothek

SPRC264 — TMS320C5000/6000-Bildbibliothek (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Benutzerhandbuch: PDF
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Treiber oder Bibliothek

TELECOMLIB — Telekommunikations- und Medienbibliotheken – FAXLIB, VoLIB und AEC/AER für TMS320C64x+ und TMS320C55

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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Software-Codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP-, Sprach- und Audio-Codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
Von: Adaptive Digital Technologies, Inc.
Partner-Website besuchen
Software-Codec

ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP-Telekommunikations- und Audio-Codecs

Algotron provides C5000 DSP software modules for telecoms & audio. Examples are: modem data pumps, speech coders, signal generators & detectors for DTMF and caller ID. All modules feature simple yet flexible interfaces with full re-entrancy. They come with user's guides, example (...)
Von: Algotron
Partner-Website besuchen
Software-Codec

C55XCODECS — CODECS – optimiert für C55x-Geräte

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
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Software-Codec

DSPI-3P-DSPVOIPCODECS — DSP-Innovationen: DSP-VoIP-Codecs

DSP Innovations is a supplier of C5000TM DSP-software and engineering services. Proprietary and standard vocoders from DSPINI have superior characteristics, operate in range from 300 bps up to 64 kbps and are used in: secure voice, software defined radio, wireless, VoIP, voice storage, and more. (...)
Von: DSP Innovations
Partner-Website besuchen
Software-Codec

VOCAL-3P-DSPVOIPCODECS — Vocal-Technologien DSP VoIP-Codecs

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
Von: VOCAL Technologies, Ltd.
Partner-Website besuchen
Simulationsmodell

C5504 ZCH BSDL Model

SPRM502.ZIP (5 KB) - BSDL Model
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Simulationsmodell

C5504 ZCH IBIS Model

SPRM503.ZIP (445 KB) - IBIS Model
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (ZCH) 196 Ultra Librarian
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