Información de empaque
| Encapsulado | Pines VQFN (RGE) | 24 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Empresa de transporte 3,000 | LARGE T&R |
Características para DRV8300
- 100-V Three Phase
Half-Bridge Gate driver
- Drives N-Channel MOSFETs (NMOS)
- Gate Driver Supply (GVDD): 5-20 V
- MOSFET supply (SHx) support upto 100 V
- Integrated Bootstrap Diodes (DRV8300D devices)
- Supports Inverting and Non-Inverting INLx inputs
- Bootstrap gate drive architecture
- 750-mA source current
- 1.5-A sink current
- Supports up to 15S battery powered applications
- Low leakage current on SHx pins (<55 µA)
- Absolute maximum BSTx voltage upto 125-V
- Supports negative transients upto -22-V on SHx
- Built-in cross conduction prevention
- Adjustable deadtime through DT pin for QFN package variants
- Fixed deadtime insertion of 200 nS for TSSOP package variants
- Supports 3.3-V and 5-V logic inputs with 20 V Abs max
- 4 nS typical propogation delay matching
- Compact QFN and TSSOP packages
- Efficient system design with Power Blocks
- Integrated protection features
- BST undervoltage lockout (BSTUV)
- GVDD undervoltage (GVDDUV)
Descripción de DRV8300
DRV8300 is 100-V three half-bridge gate drivers, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8300D generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the high-side MOSFETs. The DRV8300N generates the correct gate drive voltages using an external bootstrap diode and external capacitor for the high-side MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750-mA source and 1.5-A sink currents.
The phase pins SHx is able to tolerate the significant negative voltage transients; while high side gate driver supply BSTx and GHx is able to support to higher positive voltage transients (125-V) abs max voltage which improves robustness of the system. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high side through GVDD and BST undervoltage lockout.