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LSF0002

ACTIVO

Convertidor autobidireccional ultrapequeño para aplicaciones de drenaje abierto e inserción y extrac

Detalles del producto

Technology family LSF Applications GPIO, I2C, MDIO, PMBus, SMBus Bits (#) 2 Data rate (max) (Mbps) 200 High input voltage (min) (V) 0.95 High input voltage (max) (V) 5 Vout (min) (V) 0.95 Vout (max) (V) 5 Supply current (max) (µA) 12.5 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LSF Applications GPIO, I2C, MDIO, PMBus, SMBus Bits (#) 2 Data rate (max) (Mbps) 200 High input voltage (min) (V) 0.95 High input voltage (max) (V) 5 Vout (min) (V) 0.95 Vout (max) (V) 5 Supply current (max) (µA) 12.5 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
X2SON (DTQ) 6 0.8 mm² 1 x 0.8
  • Provides bidirectional voltage translation with no direction pin
  • Supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range
  • Provides bidirectional voltage translation with no direction pin
  • Supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range

The LSF0002 supports bidirectional voltage translation without the need for DIR pin, which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load, which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which makes it compatible with TTL levels in industrial and telecom applications. The LSF family can set up different voltage translation levels, which makes it very flexible.

Unlike the LSF0x0x family, the LSF0002 does not require VREF_A and VREF_B power supplies and the 200kΩ bias resistor. The LSF0002 utilizes the VBIAS pin that enables translation by being biased to the same voltage as the lower power supply at the I/Os that is being translated to and from.

The LSF0002 supports bidirectional voltage translation without the need for DIR pin, which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load, which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which makes it compatible with TTL levels in industrial and telecom applications. The LSF family can set up different voltage translation levels, which makes it very flexible.

Unlike the LSF0x0x family, the LSF0002 does not require VREF_A and VREF_B power supplies and the 200kΩ bias resistor. The LSF0002 utilizes the VBIAS pin that enables translation by being biased to the same voltage as the lower power supply at the I/Os that is being translated to and from.

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Documentación técnica

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* Data sheet LSF0002 Ultra-Small Auto-Bidirectional Translator for Open Drain or Push Pull Applications datasheet PDF | HTML 11 abr 2024

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
Placa de evaluación

LSF-EVM — Módulo de evaluación de la familia de repetidores LSF de 1 a 8 bits

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Guía del usuario: PDF
Modelo de simulación

LSF0002 IBIS Model

SDLM076.ZIP (56 KB) - IBIS Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
X2SON (DTQ) 6 Ultra Librarian

Pedidos y calidad

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  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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