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SN74AVC4T234

ACTIVO

Transceptor de bus de alimentación doble de 4 bits de con traducción de tensión configurable

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SN74AVC4T234

ACTIVO
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Detalles del producto

Technology family AVC Applications JTAG Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.9 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) -12 Supply current (max) (µA) 3.6 Features 2.8 Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications JTAG Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.9 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) -12 Supply current (max) (µA) 3.6 Features 2.8 Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZWA) 11 2.8 mm² 2 x 1.4
  • Wide operating VCC range of 0.9 V to 3.6 V
  • 3.6-V I/O Tolerant to support mixed-mode signal operation
  • Max tpd of 3.7 ns at 3.3 V
  • Balanced propagation delays: tPLH = tPHL
  • Low static-power consumption, 5-µA Max ICC
  • Outputs disabled if either VCC goes to 0V
  • ±3-mA Output drive at 1.8 V
  • 26-Ω series resistor on A-side outputs
  • Ioff supports partial power-down-mode operation
  • Input hysteresis allows slow input transition and better switching noise immunity at input
  • Maximum data rates
    • 380 Mbps (1.8-V to 3.3-V translation)
    • 200 Mbps (<1.8-V to 3.3-V translation)
    • 200 Mbps (translate to 2.5 V or 1.8 V)
    • 150 Mbps (translate to 1.5 V)
    • 100 Mbps (translate to 1.2 V)
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 500-V charged-device model (C101)
  • Wide operating VCC range of 0.9 V to 3.6 V
  • 3.6-V I/O Tolerant to support mixed-mode signal operation
  • Max tpd of 3.7 ns at 3.3 V
  • Balanced propagation delays: tPLH = tPHL
  • Low static-power consumption, 5-µA Max ICC
  • Outputs disabled if either VCC goes to 0V
  • ±3-mA Output drive at 1.8 V
  • 26-Ω series resistor on A-side outputs
  • Ioff supports partial power-down-mode operation
  • Input hysteresis allows slow input transition and better switching noise immunity at input
  • Maximum data rates
    • 380 Mbps (1.8-V to 3.3-V translation)
    • 200 Mbps (<1.8-V to 3.3-V translation)
    • 200 Mbps (translate to 2.5 V or 1.8 V)
    • 150 Mbps (translate to 1.5 V)
    • 100 Mbps (translate to 1.2 V)
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 500-V charged-device model (C101)

This 4-bit non-inverting bus transceiver uses two separate configurable power-supply rails to enable asynchronous communication between B-port inputs and A-port outputs. The A port is designed to track VCCA while the B port is designed to track VCCB. Both VCCA and VCCB are configurable from 0.9 V to 3.6 V.

The SN74AVC4T234 solution offers the industry’s low-power needs in battery-powered portable applications by ensuring both a very low static and dynamic power consumption across the entire VCC range of 0.9 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then A-side ports are in the high-impedance state.

This 4-bit non-inverting bus transceiver uses two separate configurable power-supply rails to enable asynchronous communication between B-port inputs and A-port outputs. The A port is designed to track VCCA while the B port is designed to track VCCB. Both VCCA and VCCB are configurable from 0.9 V to 3.6 V.

The SN74AVC4T234 solution offers the industry’s low-power needs in battery-powered portable applications by ensuring both a very low static and dynamic power consumption across the entire VCC range of 0.9 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then A-side ports are in the high-impedance state.
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Documentación técnica

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* Data sheet SN74AVC4T234 4-Bit Dual-Supply Bus Transceiver With Config Voltage Translation datasheet (Rev. B) 01 jul 2020
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
More literature Voltage-Level Translation Guide (Rev. H) 31 ago 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 abr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
More literature LCD Module Interface Application Clip 09 may 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 ago 1998

Diseño y desarrollo

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Modelo de simulación

SN74AVC4T234 IBIS MODEL

SCEM541.ZIP (64 KB) - IBIS Model
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NFBGA (ZWA) 11 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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