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SN74AVCH2T45

ACTIVO

Transceptor de bus de alimentación doble de 2 bits con traducción de tensión configurable y salidas

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SN74AXCH2T45 ACTIVO Transceptor de bus de alimentación doble AXC de 2 bits de 0.65 V a 3.6 V con retención de bus Pin-to-pin upgrade with a wider voltage range and improved performance

Detalles del producto

Technology family AVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 0.8 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 0.8 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree Package
  • VCC Isolation
  • 2-Rail Design
  • I/Os are 4.6 V Tolerant
  • Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs
  • Maximum Data Rates
    • 500 Mbps (1.8 V to 3.3 V)
    • 320 Mbps (< 1.8 V to 3.3 V)
    • 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 280 Mbps (Level-Shifting to 1.5 V)
    • 240 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • Available in the Texas Instruments NanoFree Package
  • VCC Isolation
  • 2-Rail Design
  • I/Os are 4.6 V Tolerant
  • Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs
  • Maximum Data Rates
    • 500 Mbps (1.8 V to 3.3 V)
    • 320 Mbps (< 1.8 V to 3.3 V)
    • 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 280 Mbps (Level-Shifting to 1.5 V)
    • 240 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The SN74AVCH2T45 features active bus-hold circuitry, which holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The SN74AVCH2T45 features active bus-hold circuitry, which holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74AVCH2T45 2-Bit, 2-Supply, Bus Transceiver with Configurable Level-Shifting and Translation and 3-State Outputs datasheet (Rev. H) PDF | HTML 15 abr 2015
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 abr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
More literature LCD Module Interface Application Clip 09 may 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 ago 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
Placa de evaluación

AVCLVCDIRCNTRL-EVM — EVM genérico para dispositivo de traducción bidireccional controlado por dirección compatible con AV

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

Guía del usuario: PDF
Modelo de simulación

SN74AVCH2T45 IBIS Model (Rev. B)

SCEM433B.ZIP (118 KB) - IBIS Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

Pedidos y calidad

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  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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