Información de empaque
| Encapsulado | Pines SOIC (DW) | 24 |
| Rango de temperatura de funcionamiento (℃) -40 to 85 |
| Cant. de paquetes | Empresa de transporte 2,000 | LARGE T&R |
Características para SN74LVC828A
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.7 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Descripción de SN74LVC828A
This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2)\ input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at its outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.