CDCE6214

Name: CDCE6214
Brand: TI
SKU: CDCE6214
Price: 2.1 USD

활성

PLL 1개, 차동 출력 4개를 지원하는 초저전력 클록 생성기

지금 주문

데이터 시트

document-pdfAcrobat CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet (영어) PDF | HTML

CDCE6214

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Clock generator

Number of outputs

4

Output frequency (max) (MHz)

350

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Input type

LVCMOS, Universal input, XTAL

Output type

HCSL, LVCMOS, LVDS

Operating temperature range (°C)

-40 to 105

Features

I2C, Integrated EEPROM, Pin programmable, Serial interface

Rating

Catalog

Function

Clock generator

Number of outputs

4

Output frequency (max) (MHz)

350

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Input type

LVCMOS, Universal input, XTAL

Output type

HCSL, LVCMOS, LVDS

Operating temperature range (°C)

-40 to 105

Features

I2C, Integrated EEPROM, Pin programmable, Serial interface

Rating

Catalog

VQFN (RGE)

24

16 mm² 4 x 4

Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F_out > 100 MHz) as:
- Integer mode:
  - Differential output: 350 fs typical, 600 fs maximum
  - LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
  - Differential output: 1.7 ps typical, 2.1 ps maximum
  - LVCMOS output: 2.0 ps typical, 4.0 ps maximum
Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
2.335-GHz to 2.625-GHz internal VCO
Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
Flexible output clock distribution
- 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
Configurable GPIOs and flexible configuration options
- I²C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
Supports 100-Ω systems
Low electromagnetic emissions
Small footprint: 24-pin VQFN (4 mm × 4 mm)

Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F_out > 100 MHz) as:
- Integer mode:
  - Differential output: 350 fs typical, 600 fs maximum
  - LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
  - Differential output: 1.7 ps typical, 2.1 ps maximum
  - LVCMOS output: 2.0 ps typical, 4.0 ps maximum
Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
2.335-GHz to 2.625-GHz internal VCO
Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
Flexible output clock distribution
- 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
Configurable GPIOs and flexible configuration options
- I²C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
Supports 100-Ω systems
Low electromagnetic emissions
Small footprint: 24-pin VQFN (4 mm × 4 mm)

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I²C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I²C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

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관심 가지실만한 유사 제품

open-in-new

대안 비교

다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능

LMK5B12204

활성

네트워크 동기화 및 BAW 기술을 지원하는 초저지터 클록 제너레이터 This product has more robust jitter performance and built-in network synchronization capabilities.

기술 자료

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=TI에서 선정한 이 제품의 인기 문서

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3개 모두 보기

	유형	직함		날짜
*	Data sheet	CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet	PDF \| HTML	2020/07/02
	Application note	Clocking for PCIe Applications	PDF \| HTML	2023/11/28
	User guide	CDCE6214-Q1 Registers (Rev. B)		2019/11/27

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

CDCE6214-Q1EVM — 차동 출력 4개 및 LVCMOS 출력 1개 클록 생성기 평가 모듈

CDCE6214-Q1 평가 모듈(EVM)은 CDCE6214-Q1 초저전력 클록 발생기용 평가 플랫폼입니다. 이
평가 모듈은 I²C 버스에 액세스하여 CDCE6214-Q1과 통신하기 위한 USB 기반 인터페이스를 제공합니다. 핀 제어 모드는 디바이스를 특정 작동 모드로 설정할 수 있습니다.

사용 설명서: PDF

TI.com에서 구매 불가

설계 툴

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

지금 설계하기

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)

요청

패키지	핀	CAD 기호, 풋프린트 및 3D 모델
VQFN (RGE)	24	Ultra Librarian

TI의 평가 항목에 대한 표준 약관이 적용됩니다.

CDCE6214

PLL 1개, 차동 출력 4개를 지원하는 초저전력 클록 생성기

CDCE6214

제품 상세 정보

관심 가지실만한 유사 제품

다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능

기술 자료

설계 및 개발

CDCE6214-Q1EVM — 차동 출력 4개 및 LVCMOS 출력 1개 클록 생성기 평가 모듈

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

주문 및 품질

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

비디오 시리즈

동영상