ADC12D1620QML-SP
- Total ionizing dose (TID) to 300 krad(Si)
- Single event functional interrupt (SEFI) tested
- Single event latch-up (SEL) > 120 MeV-cm2/mg
- Cold sparing capable
- Wide temperature range –55°C to +125°C
- Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
- 3-dB Input bandwidth = 3 GHz
- Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
- Auto-sync function for multi-chip systems
- Time stamp feature to capture external trigger
- Test patterns at output for system debug
- 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
- Single 1.9-V power supply
The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.
技術文件
設計與開發
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TSW12D1620EVM-CVAL — ADC12D1620QML-SP 航太級寬頻接收器評估模組
TSW12D1620EVM-CVAL 是 1.5-GHz 寬頻接收器評估模組 (EVM),其中包括放大器、類比轉數位轉換器 (ADC)、時脈、溫度感測器、微控制器及電源解決方案的陶瓷工程模型。電路板最適合從近 DC 到 1.5 GHz 的 IF/RF 頻率數位化。
類比輸入路徑可選擇將 6.5-GHz LMH5401-SP 做為單端至差動增益區塊,或繞過放大器並以差動訊號驅動 ADC。放大器後則為 12 位元、雙 1.6-GSPS 或單 3.2-GSPS ADC12D1620QML-SP。這些高效能元件皆有必要的電源、微控制器和溫度感測器裝置支援。
TSW12D1620EVM-CVAL (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TIDA-070004 — 採用整合式數位輸出溫度感測器的航太級參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
CCGA (NAA) | 376 | Ultra Librarian |
CLGA (FVA) | 256 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。