LF398-N
- Operates from ±5-V to ±18-V Supplies
- Less than 10-µs Acquisition Time
- Logic Input Compatible With TTL, PMOS, CMOS
- 0.5-mV Typical Hold Step at Ch = 0.01 µF
- Low Input Offset
- 0.002% Gain Accuracy
- Low Output Noise in Hold Mode
- Input Characteristics Do Not Change During Hold Mode
- High Supply Rejection Ratio in Sample or Hold
- Wide Bandwidth
- Space Qualified, JM38510
The LFx98x devices are monolithic sample-and-hold circuits that use BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LFx98x to be included inside the feedback loop of 1-MHz operational amplifiers without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1-µF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feedthrough from input to output in the hold mode, even for input signals equal to the supply voltages.
Logic inputs on the LFx98x are fully differential with low input current, allowing for direct connection to TTL, PMOS, and CMOS. Differential threshold is
1.4 V. The LFx98x will operate from ±5-V to ±18-V supplies.
An A version is available with tightened electrical specifications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LFx98x Monolithic Sample-and-Hold Circuits datasheet (Rev. C) | PDF | HTML | 2018年 10月 5日 |
| Application note | AN-298 Isolation Techniques for Signal Conditioning (Rev. B) | 2013年 5月 6日 | ||
| Application note | AN-301 Signal Conditioning for Sophisticated Transducers (Rev. B) | 2013年 5月 6日 | ||
| Application note | Applications of the LM3524 Pulse Width Modulator (Rev. B) | 2013年 4月 23日 | ||
| Application note | Using ADC0808/809 8-Bit uP Compble ADCs w/8-Chan Analog Multiplexr (Rev. B) | 2013年 4月 22日 | ||
| More literature | Die D/S LF398 MDC Monolithic Sample And Hold Circuit | 2012年 9月 7日 | ||
| Application note | Data Acq Using ADC0816 & ADC0817 8-Bit ADC w/On-Chip 16 Chan Multiplexr | 2004年 5月 10日 | ||
| Application note | AN-294 Special Sample and Hold Techniques | 2004年 5月 10日 | ||
| Application note | Specifications and Architectures of Sample-and-Hold Amplifiers | 2004年 5月 3日 | ||
| Application note | Freq-to-Vltg Converter Uses Sample-and-Hold to Improve Response & Ripple | 2002年 10月 3日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PDIP (P) | 8 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點