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電壓轉換閘極

SN74LV1T00

現行

單電源雙輸入正 NAND 閘邏輯電平移位器

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產品規格表

SN74LV1T00

現行
產品規格表 立即訂購

產品詳細資料

Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 10 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 10 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Single-supply voltage translator at 5.0/3.3/2.5/1.8V VCC
  • Operating range of 1.8V to 5.5V
    • Up translation:
      • 1.2V1 to 1.8V
      • 1.5V1 to 2.5V
      • 1.8V1 to 3.3V
      • 3.3V1 to 5.0V
    • Down translation:
      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Logic output is referenced to VCC
  • Output drive
    • 8mA output drive at 5V
    • 7mA output drive at 3.3V
    • 3mA output drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65mm
  • Latch-up performance exceeds 250mA order number package body size per JESD 17
  • Supports standard Logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families
  • Single-supply voltage translator at 5.0/3.3/2.5/1.8V VCC
  • Operating range of 1.8V to 5.5V
    • Up translation:
      • 1.2V1 to 1.8V
      • 1.5V1 to 2.5V
      • 1.8V1 to 3.3V
      • 3.3V1 to 5.0V
    • Down translation:
      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Logic output is referenced to VCC
  • Output drive
    • 8mA output drive at 5V
    • 7mA output drive at 3.3V
    • 3mA output drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65mm
  • Latch-up performance exceeds 250mA order number package body size per JESD 17
  • Supports standard Logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families

SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels

The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors.

The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels

The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors.

The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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類型 標題 日期
* Data sheet SN74LV1T00 Single Power Supply 2-Input Positive NAND Gate CMOS Logic Level Shifter datasheet (Rev. E) PDF | HTML 2024年 7月 25日
Application note LV1T Family of single supply translators (Rev. B) PDF | HTML 2022年 12月 16日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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模擬型號

SN74LV1T00 Behavioral SPICE Model

SCLM187.ZIP (7 KB) - PSpice Model
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模擬型號

SN74LV1T00 IBIS Model (Rev. A)

SCLM103A.ZIP (43 KB) - IBIS Model
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參考設計

TIDA-01040 — 適合高電流應用的電池測試器參考設計

Li-Ion battery formation and electrical testing require accurate voltage and current control, usually to better than ±0.05% over the specified temperature range.  This reference design proposes a solution for high-current (up to 50 A) battery tester applications supporting input (bus) (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01041 — 適合多相高精密度 0.5 至 100A 電池化成作業的電池測試器參考設計

This reference design provides a multi-phase solution for a wide range of current battery test applications. Leveraging the dual phase buck/boost controller LM5170's daisy chain configuration gives the design the ability to achieve 100A charging/discharging rates. Utilizing high accuracy constant (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01042 — 適合 50-A、100-A 及 200-A 應用的模組化電池測試器參考設計

This reference design provides a modular battery test solution allowing users to have the flexibility to test batteries at different current levels with one design. This design leverages the TIDA-01041 reference design by providing two 100-A battery testers that can work independently or be (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
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  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
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  • 組裝地點

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