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THS6062

現行

低雜訊 ADSL 雙路差分接收器

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產品規格表

THS6062

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Architecture DSL Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 33 BW at Acl (MHz) 100 Acl, min spec gain (V/V) 1 Vn at flatband (typ) (nV√Hz) 1.6 Vn at 1 kHz (typ) (nV√Hz) 1.9 Iq per channel (typ) (mA) 7.5 Vos (offset voltage at 25°C) (max) (mV) 6 Rail-to-rail No Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 95 Input bias current (max) (pA) 10000000 Offset drift (typ) (µV/°C) 20 GBW (typ) (MHz) 100 Iout (typ) (mA) 90 2nd harmonic (dBc) 91 3rd harmonic (dBc) 109 Frequency of harmonic distortion measurement (MHz) 1
Number of channels 2 Architecture DSL Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 33 BW at Acl (MHz) 100 Acl, min spec gain (V/V) 1 Vn at flatband (typ) (nV√Hz) 1.6 Vn at 1 kHz (typ) (nV√Hz) 1.9 Iq per channel (typ) (mA) 7.5 Vos (offset voltage at 25°C) (max) (mV) 6 Rail-to-rail No Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 95 Input bias current (max) (pA) 10000000 Offset drift (typ) (µV/°C) 20 GBW (typ) (MHz) 100 Iout (typ) (mA) 90 2nd harmonic (dBc) 91 3rd harmonic (dBc) 109 Frequency of harmonic distortion measurement (MHz) 1
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • ADSL Differential Receiver
  • Low 1.6 nV/)
  • 5 V, ±5 V to ±15 V Typical Operation
  • Available in Standard SOIC or MSOP PowerPAD™ Package

    • PowerPAD is a trademark of Texas Instruments.
    • ADSL Differential Receiver
    • Low 1.6 nV/)
  • 5 V, ±5 V to ±15 V Typical Operation
  • Available in Standard SOIC or MSOP PowerPAD™ Package

    • PowerPAD is a trademark of Texas Instruments.

    The THS6062 is a high-speed differential receiver designed for ADSL data communication systems. Its very low 1.6 nV/), exceeding the distortion requirements of ADSL CODECs. The THS6062 is a voltage feedback amplifier offering a high 100-MHz bandwidth and 100-V/µs slew rate and is stable at gains of 2(-1) or greater. It operates over a wide range of power supply voltages including 5 V and ±5 V to ±15 V. This device is available in standard SOIC or MSOP PowerPAD package. The small, surface-mount, thermally-enhanced MSOP PowerPAD package is fully compatible with automated surface-mount assembly procedures.

    The THS6062 is a high-speed differential receiver designed for ADSL data communication systems. Its very low 1.6 nV/), exceeding the distortion requirements of ADSL CODECs. The THS6062 is a voltage feedback amplifier offering a high 100-MHz bandwidth and 100-V/µs slew rate and is stable at gains of 2(-1) or greater. It operates over a wide range of power supply voltages including 5 V and ±5 V to ±15 V. This device is available in standard SOIC or MSOP PowerPAD package. The small, surface-mount, thermally-enhanced MSOP PowerPAD package is fully compatible with automated surface-mount assembly procedures.
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    技術文件

    star =TI 所選的此產品重要文件
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    類型 標題 日期
    * Data sheet Low-Noise ADSL Dual Differential Receiver datasheet (Rev. D) 2007年 10月 15日
    E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
    Application note Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日
    Application note Active Output Impedance for ADSL Line Drivers 2002年 11月 26日
    User guide THS6062 EVM User's Guide 1999年 1月 21日

    設計與開發

    如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

    模擬型號

    THS6062 PSpice Model (Rev. B)

    SLOJ011B.ZIP (39 KB) - PSpice Model
    下載
    模擬型號

    THS6062 TINA-TI Reference Design (Rev. B)

    SLAC108B.TSC (98 KB) - TINA-TI Reference Design
    下載
    模擬型號

    THS6062 TINA-TI Spice Model (Rev. A)

    SLAM037A.ZIP (4 KB) - TINA-TI Spice Model
    下載
    模擬工具

    PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

    PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    要求
    模擬工具

    TINA-TI — 基於 SPICE 的類比模擬程式

    TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
    使用指南: PDF
    View Options
    封裝 針腳 CAD 符號、佔位空間與 3D 模型
    HVSSOP (DGN) 8 Ultra Librarian
    SOIC (D) 8 Ultra Librarian
    適用 TI 的評估品項標準條款與條件。

    訂購與品質

    內含資訊：
    • RoHS
    • REACH
    • 產品標記
    • 鉛塗層/球物料
    • MSL 等級/回焊峰值
    • MTBF/FIT 估算值
    • 材料內容
    • 認證摘要
    • 進行中持續性的可靠性監測
    內含資訊：
    • 晶圓廠位置
    • 組裝地點

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