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微控制器 (MCU) 與處理器
數位訊號處理器 (DSP)

TMS320C6657

現行

高效能雙核心 C66x 定點和浮點 DSP - 最高 1.25GHz，2 UART

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產品規格表
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TMS320C6657

現行
產品規格表 立即訂購

產品詳細資料

DSP type 2 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
DSP type 2 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CZH) 625 441 mm² 21 x 21 FCBGA (GZH) 625 441 mm² 21 x 21
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
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類型 標題 日期
* Data sheet TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. D) PDF | HTML 2019年 9月 4日
* Errata TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) 2016年 5月 19日
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021年 6月 25日
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019年 6月 11日
Application note Keystone Bootloader Resources and FAQ 2019年 5月 29日
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019年 5月 17日
Application note Hardware Design Guide for KeyStone Devices (Rev. D) 2019年 3月 21日
Application note KeyStone I DDR3 interface bring-up 2019年 3月 6日
White paper Designing professional audio mixers for every scenario 2018年 6月 28日
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017年 7月 26日
Application note PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A) 2017年 5月 19日
Application note Processor SDK RTOS Audio Benchmark Starter Kit 2017年 4月 12日
Application note Power Consumption Summary for KeyStone C66x Devices (Rev. B) 2017年 2月 2日
Application note KeyStone I DDR3 Initialization (Rev. E) 2016年 10月 28日
Application note Keystone NDK FAQ 2016年 10月 3日
Product overview TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) 2016年 5月 23日
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016年 4月 13日
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016年 2月 23日
Application note TI DSP Benchmarking 2016年 1月 13日
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015年 8月 13日
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015年 5月 6日
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015年 4月 9日
White paper TI’s processors leading the way in embedded analytics 2015年 3月 3日
User guide DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) 2015年 1月 20日
Application note TI Keystone DSP Hyperlink SerDes IBIS-AMI Models 2014年 10月 9日
Application note TI Keystone DSP PCIe SerDes IBIS-AMI Models 2014年 10月 9日
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 4日
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 3日
More literature KeyStone Lab Manual - Training 2014年 6月 5日
User guide System Analyzer User's Guide (Rev. F) 2013年 11月 18日
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013年 9月 30日
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013年 7月 15日
White paper Accelerating high-performance computing development with Desktop Linux SDK 2013年 7月 8日
User guide C66x CorePac User's Guide (Rev. C) 2013年 6月 28日
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013年 6月 28日
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013年 5月 28日
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 2012年 11月 5日
Application note SerDes Implementation Guidelines for KeyStone I Devices 2012年 10月 31日
Product overview TMS320C66x high-performance multicore DSPs for video surveillance 2012年 9月 6日
Application note Multicore Programming Guide (Rev. B) 2012年 8月 29日
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012年 8月 21日
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012年 8月 21日
User guide Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices 2012年 7月 12日
User guide Universal Parallel Port (uPP) for KeyStone Architecture User's Guide 2012年 6月 11日
User guide Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices 2012年 5月 25日
White paper Leveraging multicore processors for machine vision applications 2012年 5月 9日
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 2012年 4月 24日
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012年 3月 30日
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 27日
White paper Superior performance at breakthrough size, weight & power 2012年 3月 26日
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 22日
White paper Maximizing Multicore Efficiency with Navigator Runtime 2012年 2月 23日
Application note PCIe Use Cases for KeyStone Devices 2011年 12月 13日
User guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) 2011年 10月 15日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
User guide Debug and Trace for KeyStone I Devices User's Guide (Rev. A) 2011年 9月 22日
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011年 9月 2日
White paper KeyStone Multicore SoC Tool Suite: one platform for all needs 2011年 6月 17日
User guide Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A) 2011年 6月 10日
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011年 5月 24日
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011年 5月 19日
Application note TMS320C66x DSP Generation of Devices (Rev. A) 2011年 4月 25日
White paper Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP 2011年 3月 16日
White paper Software-Based Ultrasound Beamforming on Multicore DSPs 2011年 3月 6日
White paper KeyStone Memory Architecture White Paper (Rev. A) 2010年 12月 21日
User guide Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide 2010年 11月 18日
User guide C66x CPU and Instruction Set Reference Guide 2010年 11月 9日
User guide C66x DSP Cache User's Guide 2010年 11月 9日
Application note Clocking Design Guide for KeyStone Devices 2010年 11月 9日
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010年 11月 9日
Application note Optimizing Loops on the C66x DSP 2010年 11月 9日
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010年 11月 9日
User guide Flip Chip Ball Grid Array Package Reference Guide (Rev. A) 2005年 5月 23日
Application note AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) 2004年 5月 1日

設計與開發

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開發板

TMDSEVM6657 — TMS320C6657 Lite 評估模組

The TMS3206657 Lite Evaluation Module (EVM), is an easy-to-use, cost-efficient development tool that helps developers quickly get started with designs using the C6657 or C6655 or C6654 family of DSPs. The EVM includes an on-board, single C6657 processor with robust connectivity options that allows (...)

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子卡

SHELD-3P-DSP-SOMS — Sheldon DSP-FPGA 主機板

Sheldon Instruments designs and manufactures DSP based, COTS data acquisition and control hardware for PCIe/PCI, PCI104e/PCI104, XMC/PMC, and CompactPCI systems, along with drivers and real time development software for a variety of applications and markets.

Learn more about Sheldon Instruments at (...)
從：Sheldon Instruments, Inc.
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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

BIOSMCSDK-C66X — SYS/BIOS MCSDK for C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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產品
數位訊號處理器 (DSP)
TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6657 — 高效能雙核心 C66x 定點和浮點 DSP - 最高 1.25GHz，2 UART TMS320C6670 — 適用通訊和電信的 4 核心定點和浮點 DSP TMS320C6678 — 高效能八核心 C66x 定點和浮點 DSP - 最高 1.25GHz
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軟體開發套件 (SDK)

PROCESSOR-SDK-C665X — 適用於 C665x 處理器的處理器 SDK - 支援 TI-RTOS

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
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驅動程式或資料庫

MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 庫 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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驅動程式或資料庫

TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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軟體轉碼器

C66XCODECS — 轉碼器 - 視訊、語音 - 適用於 C66x 架構產品

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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軟體轉碼器

VOCAL-3P-DSPVOIPCODECS — VOCAL 技術 DSP VoIP 轉碼器

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
從：VOCAL Technologies, Ltd.
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模擬型號

C6657 Power Consumption Model

SPRM600.ZIP (178 KB) - Power Model
下載
模擬型號

KeyStone I SerDes IBIS AMI Models

SPRM742.ZIP (969314 KB) - IBIS Model
lock = 需要匯出核准 (1 分鐘)
lock 下載
模擬型號

TMS320C6655/57 CYP IBIS Model (revision 1.2)

SPRM570.ZIP (415 KB) - IBIS Model
下載
模擬型號

TMS320C6657/55/54 CZH BSDL Model (Silicon Revision 1)

SPRM572.ZIP (21 KB) - BSDL Model
下載
配置圖

TMS320C6655/57 ORCAD Capture Library Files

SPRR178.ZIP (12 KB)
下載
配置圖

TMS320C6657 Thermal Model

SPRR183.ZIP (3 KB)
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參考設計

TIDEP-0099 — 適用於基於語音的應用的音訊預處理系統參考設計

This reference design uses multiple microphones, a beamforming algorithm, and other processes to extract clear speech and audio amidst noise and other clutter.  The rapid increase in applications that are used in noise-prone environments for voice activated digital assistants creates demand (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0045 — 透過 TI C6678 DSP 實作即時合成孔徑雷達 (SAR) 演算法的參考設計

This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0036 — 使用 TMS320C6657 實作高效率 OPUS 轉碼器解決方案的參考設計

The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (CZH) 625 Ultra Librarian
FCBGA (GZH) 625 Ultra Librarian
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