TMS320DM368

Name: TMS320DM368
Brand: TI
SKU: TMS320DM368
Price: 20.277 USD

現行

DaVinci 數位媒體處理器

立即訂購

產品規格表

document-pdfAcrobat TMS320DM368 Digital Media System-on-Chip (DMSoC) datasheet (Rev. C) (英文)

勘誤表

document-pdfAcrobat
TMS320DM368 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. B) (英文)

TMS320DM368

現行

產品規格表

立即訂購

產品詳細資料

DSP type

Operating system

Linux

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSP type

Operating system

Linux

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 85

NFBGA (ZCE)

338

169 mm² 13 x 13

Highlights
- High-Performance Digital Media System-on-Chip (DMSoC)
- 432-MHz ARM926EJ-S Clock Rate
- Two Video Image Co-processors (HDVICP, MJCP) Engines
- Supports a Range of Encode, Decode and Video Quality Operations
- Video Processing Subsystem
  - HW Face Detect Engine
  - Resize Engine from 1/16x to 8x
  - 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
  - 4:2:2 (8-/16-bit) Interface
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - Hardware On-Screen Display (OSD)
- Capable of 1080p 30fps H.264 video processing
- Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
- 8 Different Boot Modes and Configurable Power-Saving Modes
- Pin-to-pin and software compatible with DM365
- Extended temperature (-40°C - 85°C) available
- 3.3-V and 1.8-V I/O, 1.35-V Core
- 338-Pin Ball Grid Array at 65nm Process Technology
High-Performance Digital Media System-on-Chip (DMSoC)
- 432-MHz ARM926EJ-S Clock Rate
- 4:2:2 (8-/16-Bit) Interface
- Capable of 1080p 30fps H.264 video processing
- Pin compatible with DM365 processors
- Fully Software-Compatible With ARM9™
- Extended temperature available for 432-Mhz device
ARM926EJ-S™ Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Javelle® Technology
- Embedded ICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 16K-Byte ROM
- Little Endian
Two Video Image Co-processors (HDVICP, MJCP) Engines
- Support a Range of Encode and Decode Operations
- H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
Video Processing Subsystem
- Front End Provides:
  - HW Face Detect Engine
  - Hardware IPIPE for Real-Time Image Processing
    - Resize Engine
      - Resize Images From 1/16x to 8x
      - Separate Horizontal/Vertical Control
      - Two Simultaneous Output Paths
  - IPIPE Interface (IPIPEIF)
  - Image Sensor Interface (ISIF) and CMOS Imager Interface
  - 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
  - Glueless Interface to Common Video Decoders
  - BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Histogram Module
  - Lens distortion correction module (LDC)
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - LCD Controller
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
Analog-to-Digital Convertor (ADC)
Power Management and Real Time Clock Subsystem (PRTCSS)
- Real Time Clock
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
Key Scan
Voice Codec
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - 16 MB NOR Flash, SRAM
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia/xD
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 High-Speed Device
- USB 2.0 High-Speed Host (mini-host, supporting one external device)
- USB On The Go (HS-USB OTG)
Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Two UARTs (One fast UART with RTS and CTS Flow Control)
Five Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit(I²C) Bus™
One Multi-Channel Buffered Serial Port (McBSP)
- I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Direct Interface to T1/E1 Framers
- Time Division Multiplexed Mode (TDM)
- 128 Channel Mode
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
Boot Modes
- On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
- AEMIF (NOR and OneNAND)
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
65nm Process Technology
3.3-V and 1.8-V I/O, 1.35-V Internal
Community Reesources
- TI E2E Community
- TI Embedded Processors Wiki

All trademarks are the property of their respective owners.

Highlights
- High-Performance Digital Media System-on-Chip (DMSoC)
- 432-MHz ARM926EJ-S Clock Rate
- Two Video Image Co-processors (HDVICP, MJCP) Engines
- Supports a Range of Encode, Decode and Video Quality Operations
- Video Processing Subsystem
  - HW Face Detect Engine
  - Resize Engine from 1/16x to 8x
  - 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
  - 4:2:2 (8-/16-bit) Interface
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - Hardware On-Screen Display (OSD)
- Capable of 1080p 30fps H.264 video processing
- Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
- 8 Different Boot Modes and Configurable Power-Saving Modes
- Pin-to-pin and software compatible with DM365
- Extended temperature (-40°C - 85°C) available
- 3.3-V and 1.8-V I/O, 1.35-V Core
- 338-Pin Ball Grid Array at 65nm Process Technology
High-Performance Digital Media System-on-Chip (DMSoC)
- 432-MHz ARM926EJ-S Clock Rate
- 4:2:2 (8-/16-Bit) Interface
- Capable of 1080p 30fps H.264 video processing
- Pin compatible with DM365 processors
- Fully Software-Compatible With ARM9™
- Extended temperature available for 432-Mhz device
ARM926EJ-S™ Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Javelle® Technology
- Embedded ICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 16K-Byte ROM
- Little Endian
Two Video Image Co-processors (HDVICP, MJCP) Engines
- Support a Range of Encode and Decode Operations
- H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
Video Processing Subsystem
- Front End Provides:
  - HW Face Detect Engine
  - Hardware IPIPE for Real-Time Image Processing
    - Resize Engine
      - Resize Images From 1/16x to 8x
      - Separate Horizontal/Vertical Control
      - Two Simultaneous Output Paths
  - IPIPE Interface (IPIPEIF)
  - Image Sensor Interface (ISIF) and CMOS Imager Interface
  - 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
  - Glueless Interface to Common Video Decoders
  - BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Histogram Module
  - Lens distortion correction module (LDC)
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - LCD Controller
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
Analog-to-Digital Convertor (ADC)
Power Management and Real Time Clock Subsystem (PRTCSS)
- Real Time Clock
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
Key Scan
Voice Codec
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - 16 MB NOR Flash, SRAM
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia/xD
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 High-Speed Device
- USB 2.0 High-Speed Host (mini-host, supporting one external device)
- USB On The Go (HS-USB OTG)
Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Two UARTs (One fast UART with RTS and CTS Flow Control)
Five Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit(I²C) Bus™
One Multi-Channel Buffered Serial Port (McBSP)
- I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Direct Interface to T1/E1 Framers
- Time Division Multiplexed Mode (TDM)
- 128 Channel Mode
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
Boot Modes
- On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
- AEMIF (NOR and OneNAND)
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
65nm Process Technology
3.3-V and 1.8-V I/O, 1.35-V Internal
Community Reesources
- TI E2E Community
- TI Embedded Processors Wiki

All trademarks are the property of their respective owners.

Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI).

The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368.

Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

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	類型	標題		日期
*	Data sheet	TMS320DM368 Digital Media System-on-Chip (DMSoC) datasheet (Rev. C)		2011年 6月 30日
*	Errata	TMS320DM368 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. B)		2011年 7月 11日
	Application note	High-Speed Interface Layout Guidelines (Rev. J)	PDF \| HTML	2023年 2月 24日
	White paper	Low-latency design considerations for video-enabled aerial drones		2016年 9月 15日
	EVM User's guide	TMS320DM368 Evaluation Module User's Guide		2016年 8月 3日
	User guide	TMS320DM36x DaVinci™ Video Processing Front End (VPFE) User's Guide (Rev. C)		2016年 6月 30日
	Application note	TMS320DM368 Power Consumption Summary (Rev. A)		2013年 9月 12日
	User guide	Powering the TMS320DM368 with the TPS650061		2012年 5月 8日
	Analog Design Journal	Converting single-ended video to differential video in single-supply systems		2011年 9月 16日
	User guide	TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem User's Guide (Rev. B)		2011年 8月 3日
	User guide	TMS320DM36x DMSoC General-Purpose Input/Output User's Guide (Rev. C)		2011年 1月 19日
	User guide	TMS320DM36x DMSoC Ethernet Media Access Controller (EMAC) User's Guide (Rev. B)		2010年 12月 23日
	User guide	TMS320DM36x DMSoC Video Processing Front End User's Guide (Rev. C)		2010年 11月 12日
	User guide	TMS320DM36x DMSoC Video Processing Back End User's Guide (Rev. C)		2010年 8月 26日
	User guide	TMS320DM36x DMSoC Voice Codec User's Guide (Rev. B)		2010年 7月 30日
	User guide	TMS320DM36x DMSoC Face Detection User's Guide (Rev. A)		2010年 7月 21日
	User guide	TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C)		2010年 4月 23日
	User guide	TMS320DM36x DMSoC Multimedia Card/Secure Digital Card Controller User's Guide (Rev. B)		2010年 4月 23日
	Application note	Migrating from TMS320DM365 to TMS320DM368		2010年 4月 11日
	More literature	TMS320DM3x DaVinci Video Processors		2010年 4月 11日
	User guide	TMS320DM36x DMSoC Key Scan User's Guide (Rev. A)		2010年 3月 1日
	User guide	TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (Rev. B)		2010年 3月 1日
	User guide	TMS320DM36x DMSoC Universal Host Port Interface User's Guide (Rev. A)		2009年 8月 9日
	User guide	TMS320DM36x DMSoC ARM Subsystem Reference Guide (Rev. A)		2009年 8月 7日
	User guide	TMS320DM36x DMSoC Inter-Integrated Circuit User's Guide (Rev. A)		2009年 8月 7日
	User guide	TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A)		2009年 8月 7日
	User guide	TMS320DM36x DMSoC Universal Serial Bus User's Guide (Rev. A)		2009年 8月 7日
	Application note	TMS320DM36x SoC Architecture and Throughput		2009年 7月 29日
	User guide	TMS320DM36x DMSoC Analog to Digital Converter User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC DDR2/mDDR Memory Controller User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC Enhanced Direct Memory Access Controller User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC Pulse-Width Modulator User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC Real Time Out User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide		2009年 3月 3日
	User guide	TMS320DM36x DMSoC Universal Asynchronous Receiver/Transmitter User's Guide		2009年 3月 3日
	Application note	Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)		2008年 7月 17日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TMDXEVM368 — TMS320DM36x 評估模組

The TMS320DM36x Digital Video Evaluation Module (DVEVM) enables developers to start immediate evaluation of TI’s Digital Media (DMx) processors and begin building digital video applications such as IP security cameras, action cameras, drones, wearables, digital signage, video doorbells, and (...)

使用指南: PDF

TI.com 無法提供

偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

TI.com 無法提供

偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

TI.com 無法提供

偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

TI.com 無法提供

軟體開發套件 (SDK)

LINUXDVSDK-DM36X — 用於 DM365、DM368 數位媒體處理器的 Linux 數位視訊軟體開發套件 (DVSDK)

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci™ system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the DaVinci platform. Each DVSDK combines a pre-tested set of operating system, application (...)

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軟體轉碼器

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支援產品和硬體

產品

數位訊號處理器 (DSP)

TMS320DM365 — DaVinci 數位媒體處理器

TMS320DM368 — DaVinci 數位媒體處理器

下載選項

模擬型號

DM368 ZCE BSDL Model

SPRM495.ZIP (9 KB) - BSDL Model

下載

模擬型號

DM368 ZCE IBIS Model (Rev. A)

SPRM494A.ZIP (502 KB) - IBIS Model

下載

封裝	針腳	CAD 符號、佔位空間與 3D 模型
NFBGA (ZCE)	338	Ultra Librarian

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影片系列

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TMS320DM368

DaVinci 數位媒體處理器

TMS320DM368

產品詳細資料

透過第三方提供支援

技術文件

設計與開發

TMDXEVM368 — TMS320DM36x 評估模組

TMDSEMU200-U — XDS200 USB 偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

LINUXDVSDK-DM36X — 用於 DM365、DM368 數位媒體處理器的 Linux 數位視訊軟體開發套件 (DVSDK)

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

支援產品和硬體

產品

數位訊號處理器 (DSP)

DM368 ZCE BSDL Model

DM368 ZCE IBIS Model (Rev. A)

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

影片系列

影片

下載選項

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

數位訊號處理器 (DSP)

文件

版本資訊