Produktdetails

2nd harmonic (dBc) -73 3rd harmonic (dBc) -80 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.5 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 4500 Gain (max) (dB) 26 Gain (min) (dB) -6 Step size (dB) 1 Type RF VGA Iq per channel (typ) (mA) 69 Number of channels 1 Rating Catalog Operating temperature range (°C) -40 to 85 Slew rate (typ) (V/µs) 18200 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4 Vs (min) (V) 4 Vs (max) (V) 5
2nd harmonic (dBc) -73 3rd harmonic (dBc) -80 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.5 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 4500 Gain (max) (dB) 26 Gain (min) (dB) -6 Step size (dB) 1 Type RF VGA Iq per channel (typ) (mA) 69 Number of channels 1 Rating Catalog Operating temperature range (°C) -40 to 85 Slew rate (typ) (V/µs) 18200 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4 Vs (min) (V) 4 Vs (max) (V) 5
UQFN-HR (RMZ) 16 9 mm² 3 x 3
  • 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
  • Gain Range: –6 dB to 26 dB in 1-dB Steps
  • Differential Input Impedance: 100 Ω
  • Differential Output with Common-Mode Control
  • Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
    • 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
    • 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
    • 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
    • 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
  • Output IP3:
    • 43 dBm at 200 MHz
    • 33 dBm at 1 GHz
    • 27 dBm at 2 GHz
  • Output IP2:
    • 67 dBm at 200 MHz
    • 60 dBm at 1 GHz
    • 52 dBm at 2 GHz
  • 8-dB Noise Figure at 1 GHz, RS = 100 Ω
  • 82-ps Rise, Fall Time Pulse Response
  • Supply Operation: 5.0 V at 69 mA
  • Supports Single- and (±) Split-Supply Operation:
    • DC- and AC-Coupled Applications
  • Fabricated on an Advanced Complementary BiCMOS Process
  • 3-mm × 3-mm UQFN-16 Package
  • 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
  • Gain Range: –6 dB to 26 dB in 1-dB Steps
  • Differential Input Impedance: 100 Ω
  • Differential Output with Common-Mode Control
  • Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
    • 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
    • 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
    • 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
    • 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
  • Output IP3:
    • 43 dBm at 200 MHz
    • 33 dBm at 1 GHz
    • 27 dBm at 2 GHz
  • Output IP2:
    • 67 dBm at 200 MHz
    • 60 dBm at 1 GHz
    • 52 dBm at 2 GHz
  • 8-dB Noise Figure at 1 GHz, RS = 100 Ω
  • 82-ps Rise, Fall Time Pulse Response
  • Supply Operation: 5.0 V at 69 mA
  • Supports Single- and (±) Split-Supply Operation:
    • DC- and AC-Coupled Applications
  • Fabricated on an Advanced Complementary BiCMOS Process
  • 3-mm × 3-mm UQFN-16 Package

The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).

Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.

Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.

This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.

The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).

Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.

Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.

This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier datasheet (Rev. A) PDF | HTML 19 Mai 2015
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mär 2017
Application note ADC32RF45: Amplifier to ADC Interface (Rev. A) 07 Sep 2016
Technical article Disentangle RF amplifier specs: output voltage/current and 1dB compression point PDF | HTML 09 Jun 2016
Technical article Disentangle RF amplifier specs: intermodulation distortion and intercept points PDF | HTML 19 Apr 2016
Technical article Disentangling RF amplifier specs: amplifier spot noise vs. noise figure PDF | HTML 05 Feb 2016
EVM User's guide TSW54J60 Evaluation Module User's Guide (Rev. A) 21 Sep 2015
EVM User's guide LMH6401 EVM User's Guide (Rev. A) 29 Mai 2015

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

LMH6401EVM — LMH6401-Evaluierungsmodul

The LMH6401 Evaluation module (EVM) is used to evaluate the single LMH6401, digitally-controlled variable-gain amplifier (DVGA) in a 16-lead high-performance RF package.  The EVM is designed to quickly and easily demonstrate the functionality and performance of LMH6401 across all the gain (...)

Benutzerhandbuch: PDF
GUI für Evaluierungsmodul (EVM)

SBOC451 LMH6401EVM GUI

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

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HF-VGAs
LMH6401 Digitaler Ultrabreitband-Verstärker mit variabler Verstärkung, 4,5 GHz
Hardware-Entwicklung
Evaluierungsplatine
LMH6401EVM LMH6401-Evaluierungsmodul
Simulationsmodell

LMH6401 IBIS MODEL

SNOM552.ZIP (21 KB) - IBIS Model
Simulationsmodell

LMH6401 PSpice Model

SBOMBQ6.ZIP (67 KB) - PSpice Model
Simulationsmodell

LMH6401 TINA-TI Reference Design (Rev. A)

SBOM939A.TSC (58 KB) - TINA-TI Reference Design
Simulationsmodell

LMH6401 TINA-TI Spice Model

SBOM938.ZIP (14 KB) - TINA-TI Spice Model
Referenzdesigns

TIDA-01022 — Referenzdesign für flexibles Mehrkanal-AFE mit 3,2 GSPS für DSOs, Radar und drahtlose 5G-Prüfgeräte

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-01028 — Referenzdesign für analoges Frontend mit 12,8 GSPS für Highspeed-Oszilloskope und Digitalisierer mit

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-010128 — Skalierbares 20,8-GSPS-Referenzdesign für Digitalisierer mit 12 Bit

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-010122 — Referenzdesign zur Synchronisierung von Datenwandler-DDC- und NCO-Funktionen für Mehrkanal-HF-System

Dieses Referenzdesign befasst sich mit den Herausforderungen im Zusammenhang mit dem Synchronisierungsdesign von aufkommenden 5G-adaptierten Anwendungen, wie z. B. mMIMO (Massive Multiple Input Multiple Output), Phase-Array-Radar und Kommunikationsnutzlast. Das typische HF-Frontend enthält eine (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00823 — 16 Bit, 1 GSPS, Digitalisierer-Referenzdesign mit AC- und DC-gekoppeltem Verstärker mit fester Verst

This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00826 — 50-Ohm-2-GHz-Oszilloskop-Frontend – Referenzdesign

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00822 — 16 Bit, 1 GSPS, Digitalisierer-Referenzdesign mit AC- und DC-gekoppeltem Verstärker mit variabler Ve

This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00654 — Kaskadierter LMH5401 und LMH6401 – Referenzdesign

Das Referenzdesign zeigt die breitbandige Umwandlung von unsymmetrischen zu differenziellen Signalen sowohl in DC- als auch AC-gekoppelten Anwendungen. Das Design bewertet die Leistung der Kaskade LMH5401 und LMH6401 und bietet Einblicke in das Design.
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
UQFN-HR (RMZ) 16 Ultra Librarian

Bestellen & Qualität

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  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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