Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 28 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 50 | TUBE |
Merkmale von SN65LVDS150
- A Member of the MuxItTM Serializer- Deserializer Building-Block Chip Family
- Pin Selectable Frequency Multiplier Ratios Between 4 and 40
- Input Clock Frequencies From 5 to 50 MHz
- Multiplied Clock Frequencies up to 400MHz
- Internal Loop Filters and Low PLL-Jitter of 20 ps RMS Typical at 200 MHz
- LVDS Compatible Differential Inputs and Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644-A
- LVTTL Compatible Inputs Are 5 V Tolerant
- LVDS Inputs and Outputs ESD Protection Exceeds 12 kV HBM
- Operates From a Single 3.3 V Supply
- Packaged in 28-Pin Thin Shrink Small-Outline Package With 26 mil Terminal Pitch
Muxlt is a trademark of Texas Instruments.
Beschreibung von SN65LVDS150
The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS (TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152 Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are needed. A PLL lock indicator output is available which may be used to enable link data transfers.
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the source end of the link, or by the link clock when at the destination end of the link. The differential clock reference input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended mode.
The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for transmission over the link.
An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCC is below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmax parameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and M.