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SN74AVC16T245-Q1

AKTIV

Bus-Transceiver für die Automobilindustrie, 16 Bit, Doppelversorgung, mit konfigurierbarer Spannungs

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SN74AVC16T245-Q1

AKTIV
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Produktdetails

Technology family AVC Applications RGMII Bits (#) 16 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 60 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family AVC Applications RGMII Bits (#) 16 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 60 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H3B (JESD 22 A114-A)
    • Device CDM ESD Classification Level C5 (JESD 22 C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6V Tolerant
  • Maximum Data Rates
    • 380Mbps (1.8V to 3.3V Translation)
    • 200Mbps (<1.8V to 3.3V Translation)
    • 200Mbps (Translate to 2.5V or 1.8V)
    • 150Mbps (Translate to 1.5V)
    • 100Mbps (Translate to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H3B (JESD 22 A114-A)
    • Device CDM ESD Classification Level C5 (JESD 22 C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6V Tolerant
  • Maximum Data Rates
    • 380Mbps (1.8V to 3.3V Translation)
    • 200Mbps (<1.8V to 3.3V Translation)
    • 200Mbps (Translate to 2.5V or 1.8V)
    • 150Mbps (Translate to 1.5V)
    • 100Mbps (Translate to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II

The SN74AVC16T245-Q1 is a 16-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The SN74AVC16T245-Q1 is optimized to operate with VCCA or VCCB set at 1.4V to 3.6V. It is operational with VCCA or VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC16T245-Q1 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses effectively are isolated.

The SN74AVC16T245-Q1 is a 16-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The SN74AVC16T245-Q1 is optimized to operate with VCCA or VCCB set at 1.4V to 3.6V. It is operational with VCCA or VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC16T245-Q1 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses effectively are isolated.
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Typ Titel Datum
* Data sheet SN74AVC16T245-Q1 16-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. B) PDF | HTML 01 Mär 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
More literature Automotive Logic Devices Brochure 27 Aug 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature LCD Module Interface Application Clip 09 Mai 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 Mai 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

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