CD54HC646

ACTIVO

Transceptor de bus octal sin inversión CMOS Logic de alta velocidad con salidas de 3 estados

Detalles del producto

Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family HC Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family HC Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 24 425.45 mm² 31.75 x 13.4
  • 2-V to 6-V VCC Operation (CD54HC646)
  • 4.5-V to 5.5-V VCC Operation (CD74HCT646)
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 15 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible (CD74HCT646)
  • Independent Registers for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • True Data Paths

  • 2-V to 6-V VCC Operation (CD54HC646)
  • 4.5-V to 5.5-V VCC Operation (CD74HCT646)
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 15 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible (CD74HCT646)
  • Independent Registers for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • True Data Paths

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Documentación técnica

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Tipo Título Fecha
* Data sheet CD54HC646, CD74HCT646 datasheet (Rev. B) 25 abr 2003
* SMD CD54HC646 SMD 5962-86885 21 jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 may 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 abr 1996

Diseño y desarrollo

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