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LSF0102

ACTIVO

Convertidor de nivel multivoltaje de tensión bidireccional doble

Detalles del producto

Technology family LSF Applications GPIO, I2C, MDIO, PMBus, SMBus Bits (#) 2 Data rate (max) (Mbps) 200 High input voltage (min) (V) 0.95 High input voltage (max) (V) 5 Vout (min) (V) 0.95 Vout (max) (V) 5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 12.5 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LSF Applications GPIO, I2C, MDIO, PMBus, SMBus Bits (#) 2 Data rate (max) (Mbps) 200 High input voltage (min) (V) 0.95 High input voltage (max) (V) 5 Vout (min) (V) 0.95 Vout (max) (V) 5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 12.5 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZT) 8 1.9404 mm² 1.98 x 0.98 SOT-23-THN (DDF) 8 8.12 mm² 2.9 x 2.8 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1 X2SON (DQE) 8 1.4 mm² 1.4 x 1 X2SON (DTM) 8 1.08 mm² 0.8 x 1.35
  • Provides bidirectional voltage translation with no direction pin
  • Supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range
  • Provides bidirectional voltage translation with no direction pin
  • Supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range

The LSF family of devices supports bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels which makes it very flexible.

The LSF family of devices supports bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels which makes it very flexible.

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Documentación técnica

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* Data sheet LSF0102 2 Channel Auto-Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Applications datasheet (Rev. B) PDF | HTML 11 abr 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
Application brief Enabling AI Accelerators with Voltage Level Translation PDF | HTML 01 may 2024
Application brief Integrated vs. Discrete Open Drain Level Translation PDF | HTML 09 ene 2024
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 05 sep 2023
Product overview Enabling System on Module Industrial PC Connectivity With Level Translation PDF | HTML 03 abr 2023
Application brief Enabling Next Generation Processors, FPGA, and ASSP with Voltage Level Translat PDF | HTML 17 ene 2023
Application brief Enabling Smart Solar Inverter Designs with Level Translation PDF | HTML 31 oct 2022
Product overview Translate Voltages for I2C for PCA9306 LSF0102 TXS0102 PDF | HTML 14 sep 2022
Product overview Translate Voltages for I2C PDF | HTML 02 jun 2022
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Technical article Enabling smart meter wireless connectivity with level translation PDF | HTML 23 oct 2019
Application note Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices 19 nov 2017
Application note Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators 30 oct 2017
EVM User's guide LSF-EVM Hardware User's Guide 05 jul 2017
Selection guide Logic Guide (Rev. AB) 12 jun 2017
EVM User's guide LSF010X Evaluation Module User's Guide (Rev. A) 29 jun 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 abr 2015
Application note Voltage-Level Translation With the LSF Family (Rev. B) 12 mar 2015
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
Placa de evaluación

LSF-EVM — Módulo de evaluación de la familia de repetidores LSF de 1 a 8 bits

The LSF family of devices are level translators that support a voltage range of 0.95V and 5V and provide multi-voltage bidirectional translation without a direction pin.

The LSF-EVM comes populated with the LSF0108PWR device and has landing patterns that are compatible with the LSF0101DRYR, (...)

Guía del usuario: PDF
Modelo de simulación

LSF0102 IBIS Model

SDLM023.ZIP (56 KB) - IBIS Model
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Design guide: PDF
Esquema: PDF
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Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZT) 8 Ultra Librarian
SOT-23-THN (DDF) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
X2SON (DQE) 8 Ultra Librarian
X2SON (DTM) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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