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Búferes, controladores y transceptores
Transceptores de uso general

SN54ABTH245

ACTIVO

Transceptores de bus octal con salidas de 3 estados

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SN54ABTH245

ACTIVO
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Detalles del producto

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 48 IOH (max) (mA) -24 Input type TTL Output type TTL Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 48 IOH (max) (mA) -24 Input type TTL Output type TTL Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Military Operating temperature range (°C) -55 to 125
CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so the buses are effectively isolated.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH245 is characterized for operation from -40°C to 85°C.

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so the buses are effectively isolated.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH245 is characterized for operation from -40°C to 85°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet Octal Bus Transceivers With 3-State Outputs datasheet (Rev. D) 14 sep 1999
* SMD SN54ABTH245 SMD 5962-97623 21 jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 feb 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 ene 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 mar 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

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