SN74ABT2244A

Name: SN74ABT2244A
Brand: TI
SKU: SN74ABT2244A
Price: 0.31 USD

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Búferes de 8 canales, 4,5 V a 5,5 V con entradas CMOS compatibles con TTL y salidas de 3 estados

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Hoja de datos

document-pdfAcrobat Octal Buffers And Line/MOS Drivers With 3-State Outputs datasheet (Rev. E) (Inglés)

SN74ABT2244A

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Detalles del producto

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

12

Supply current (max) (µA)

30000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

12

Supply current (max) (µA)

30000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT2240, SN74ABT2240A, and 'ABT2241, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE\) inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in.

The outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2244A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2244A is characterized for operation from -40°C to 85°C.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT2240, SN74ABT2240A, and 'ABT2241, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE\) inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in.

The outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2244A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2244A is characterized for operation from -40°C to 85°C.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	Octal Buffers And Line/MOS Drivers With 3-State Outputs datasheet (Rev. E)	01 may 1997
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 jun 2004
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)	16 feb 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 may 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 ene 2001
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)	01 mar 1997
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)	01 dic 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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