Información de empaque
| Encapsulado | Pines SOIC (D) | 16 |
| Rango de temperatura de funcionamiento (℃) 0 to 70 |
| Cant. de paquetes | Empresa de transporte 40 | TUBE |
Características para SN74ALS191A
- Single Down/Up Count-Control Line
- Look-Ahead Circuitry Enhances Speed of Cascaded Counters
- Fully Synchronous in Count Modes
- Asynchronously Presettable With Load Control
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
Descripción de SN74ALS191A
The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a
low-to-high-level transition of the clock (CLK) input if the count
enable (
) input is low.
A high at inhibits
counting. The direction of the count is determined by the level of
the down/up (D/U\) input. When D/U\ is low, the counter counts up,
and when D/U\ is high, the counter counts down.
These counters feature a fully independent clock circuit. Changes
at the control inputs ( and
D/U\) that modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the counter is
dictated solely by the conditions meeting the stable setup and hold
times.
These counters are fully programmable. Each output can be preset
to either level by placing a low on the 
input and entering the desired data at the data inputs.
The output changes to agree with the data inputs independently of the
level of the clock input. This feature allows the counters to be used
as modulo-N dividers by simply modifying the count length with the
preset inputs.
CLK, D/U\, and are buffered
to lower the drive requirement, which significantly reduces the
loading on (current required by) clock drivers, for long parallel
words.
Two outputs are available to perform the cascading function:
ripple clock and maximum/minimum count. The latter output produces a
high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is minimum (0) counting
down or maximum (15) counting up. The ripple-clock output (
) produces a low-level output pulse
under those same conditions, but only while the clock input is low.
The counter easily can be cascaded by feeding the ripple-clock output
to the enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count (MAX/MIN) output can be used to accomplish look
ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C.