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Transceptores de uso general

SN74ALVCF162835

ACTIVO

Controlador de bus universal CMOS de 18 bits y 3.3 V con salidas de 3 estados

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SN74ALVCF162835

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Detalles del producto

Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 18 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 18 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • Ideal for Use in PC133 Register DIMM
  • Typical Output Skew . . . <250 ps
  • VCC = 3.3 V ± 0.3 V . . . Normal Range
  • VCC = 2.7 V to 3.6 V . . . Extended Range
  • VCC = 2.5 V ± 0.2 V
  • Rail-to-Rail Output Swing for Increased Noise Margin
  • Balanced Output Drivers . . . ±18 mA
  • Low Switching Noise
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Ideal for Use in PC133 Register DIMM
  • Typical Output Skew . . . <250 ps
  • VCC = 3.3 V ± 0.3 V . . . Normal Range
  • VCC = 2.7 V to 3.6 V . . . Extended Range
  • VCC = 2.5 V ± 0.2 V
  • Rail-to-Rail Output Swing for Increased Noise Margin
  • Balanced Output Drivers . . . ±18 mA
  • Low Switching Noise
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 18-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).

The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 18-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).

The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Documentación técnica

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* Data sheet SN74ALVCF162835 datasheet (Rev. A) 05 ago 2004
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 ago 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 may 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Modelo de simulación

SN74ALVCF162835 IBIS Model

SCEM260.ZIP (35 KB) - IBIS Model
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TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian
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