SN74ALVCH162334

Name: SN74ALVCH162334
Brand: TI
SKU: SN74ALVCH162334
Price: 2.255 USD

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Controlador de bus universal de 16 bits con salidas de 3 estados

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document-pdfAcrobat SN74ALVCH162334 datasheet (Rev. H) (Inglés)

SN74ALVCH162334

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Detalles del producto

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

48

62.08 mm² 9.7 x 6.4

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

Widebus, EPIC are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

Widebus, EPIC are trademarks of Texas Instruments.

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V_CCoperation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V_CCoperation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	SN74ALVCH162334 datasheet (Rev. H)	24 ago 2004
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)	17 sep 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)	01 ago 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 may 2002
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	08 sep 1999
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100	03 ago 1998
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)	13 may 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 dic 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN74ALVCH162334 IBIS Model (Rev. A)

SCEM066A.ZIP (10 KB) - IBIS Model

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SSOP (DL)	48	Ultra Librarian
TSSOP (DGG)	48	Ultra Librarian
TVSOP (DGV)	48	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

SN74ALVCH162334

Controlador de bus universal de 16 bits con salidas de 3 estados

SN74ALVCH162334

Detalles del producto

Productos similares que pueden interesarle

Pin por pin con la misma funcionalidad que el dispositivo comparado

Documentación técnica

Diseño y desarrollo

SN74ALVCH162334 IBIS Model (Rev. A)

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos