The SN74F543 octal transceiver contains two sets of D-type latches
for temporary storage of data flowing in either direction. Separate
latch-enable (
or 
) and output enable (
or 
) inputs are provided for each register to permit
independent control in either direction of data flow. The A outputs
are characterized to sink 24 mA while the B outputs are characterized
to sink 64 mA.
The A-to-B enable (
)
input must be low in order to enter data from A or to output data
from B. Having low and low makes the A-to-B latches
transparent; a subsequent low-to-high transition of puts the A latches in the storage
mode. With and both low, the 3-state B outputs
are active and reflect the data present at the output of the A
latches. Data flow from B to A is similar, but requires using the
, , and inputs.
The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F543 is characterized for operation from 0°C to 70°C.
A-to-B data flow is shown; B-to-A flow control is the same
except that it uses ,
, and .
Output level before the indicated steady-state input conditions were established.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Octal Registered Transceiver With 3-State Outputs datasheet (Rev. B) | 01 oct 1993 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DB) | 24 | Ultra Librarian |
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