SN74LS221

ACTIVO

Multivibradores monoestables dobles con entradas de disparador Schmitt

Detalles del producto

Number of channels 2 Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Technology family LS Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 27000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Standard speed (tpd > 50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Technology family LS Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 27000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Standard speed (tpd > 50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8
  • Dual Versions of Highly Stable SN54121 and SN74121 One Shots
  • SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots
  • Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123
  • Overriding Clear Terminates Output Pulse
  • Dual Versions of Highly Stable SN54121 and SN74121 One Shots
  • SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots
  • Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123
  • Overriding Clear Terminates Output Pulse

The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transition- triggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, is also provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above table by choosing appropriate timing components. With Rext = 2 k and Cext = 0, an output pulse typically of 30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms.

Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed.

The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively.

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.

The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transition- triggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, is also provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above table by choosing appropriate timing components. With Rext = 2 k and Cext = 0, an output pulse typically of 30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms.

Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed.

The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively.

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.

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Documentación técnica

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Ver todo 11
Tipo Título Fecha
* Data sheet SN54221, SN54LS221, SN74221, SN74LS221 datasheet (Rev. B) 09 nov 2004
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 13 mar 2020
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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